gmacgrp_pps_control
Controls timestamp Pulse-Per-Second output
Module Instance | Base Address | Register Address |
---|---|---|
i_emac_emac0 | 0xFF800000 | 0xFF80072C |
i_emac_emac1 | 0xFF802000 | 0xFF80272C |
i_emac_emac2 | 0xFF804000 | 0xFF80472C |
Offset: 0x72C
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
trgtmodsel0 RW 0x0 |
ppsen0 RW 0x0 |
ppsctrl_ppscmd RW 0x0 |
gmacgrp_pps_control Fields
Bit | Name | Description | Access | Reset | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
6:5 | trgtmodsel0 | This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal
|
RW | 0x0 | ||||||||
4 | ppsen0 | When set low, Bits[3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD.
|
RW | 0x0 | ||||||||
3:0 | ppsctrl_ppscmd | PPSCTRL0: PPS0 Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies:
Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies.
In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example:
This behavior is because of the non-linear toggling of bits in the digital rollover mode in Register 451 (System Time - Nanoseconds Register). Flexible PPS0 Output (ptp_pps_o[0]) Control Programming these bits with a non-zero value instructs the MAC to initiate an event. Once the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically. The Software should ensure that these bits are programmed only when they are all-zero. The following list describes the values of PPSCMD0:
|
RW | 0x0 |