gmacgrp_gmii_address

          Register 4 (GMII Address Register)  

The GMII Address register controls the management cycles to the external PHY through the management interface.

Note: This register is present for all PHY interface when you select the Station Management (MDIO) feature in coreConsultant.
      
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800010
i_emac_emac1 0xFF802000 0xFF802010
i_emac_emac2 0xFF804000 0xFF804010

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_16

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

pa

RW 0x0

gr

RW 0x0

cr

RW 0x0

gw

RW 0x0

gb

RW 0x0

gmacgrp_gmii_address Fields

Bit Name Description Access Reset
31:16 reserved_31_16
Reserved
RO 0x0
15:11 pa
Physical Layer Address

This field indicates which of the 32 possible PHY devices are being accessed.
For RevMII, this field gives the PHY Address of the RevMII module.
RW 0x0
10:6 gr
GMII Register

These bits select the desired GMII register in the selected PHY device.
For RevMII, these bits select the desired CSR register in the RevMII Registers set.
RW 0x0
5:2 cr

CSR Clock Range

The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design.

The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.

  • 0000: The frequency of the CSR clock is 60-100 MHz and the MDC clock is CSR clock/42.
  • 0001: The frequency of the CSR clock is 100-150 MHz and the MDC clock is CSR clock/62.
  • 0010: The frequency of the CSR clock is 20-35 MHz and the MDC clock is CSR clock/16.
  • 0011: The frequency of the CSR clock is 35-60 MHz and the MDC clock is CSR clock/26.
  • 0100: The frequency of the CSR clock is 150-250 MHz and the MDC clock is CSR clock/102.
  • 0100: The frequency of the CSR clock is 250-300 MHz and the MDC clock is CSR clock/124.
  • 0110 and 0111: Reserved

When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range.

Program the following values only if the interfacing chips support faster MDC clocks:

  • 1000: CSR clock/4
  • 1001: CSR clock/6
  • 1010: CSR clock/8
  • 1011: CSR clock/10
  • 1100: CSR clock/12
  • 1101: CSR clock/14
  • 1110: CSR clock/16
  • 1111: CSR clock/18

These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface.

Value Description
0xa DIV8
0xb DIV10
0xc DIV12
0xd DIV14
0xe DIV16AGAIN
0xf DIV18
0x0 DIV42
0x1 DIV62
0x2 DIV16
0x3 DIV26
0x4 DIV102
0x5 DIV124
0x8 DIV4
0x9 DIV6
RW 0x0
1 gw
GMII Write

When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
0 gb
GMII Busy

This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress.

Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared.

The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0