gmacgrp_mac_frame_filter

          Register 1 (MAC Frame Filter) 

The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad Frames and Pass Control Frames.

Module Instance	Base Address	Register Address
`i_emac_emac0`	`0xFF800000`	`0xFF800004`
`i_emac_emac1`	`0xFF802000`	`0xFF802004`
`i_emac_emac2`	`0xFF804000`	`0xFF804004`

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ra` `RW 0x0`	`reserved_30_22` `RO 0x0`									`dntu` `RW 0x0`	`ipfe` `RW 0x0`	`reserved_19_17` `RO 0x0`			`vtfe` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`reserved_15_11` `RO 0x0`					`hpf` `RO 0x0`	`saf` `RW 0x0`	`saif` `RW 0x0`	`pcf` `RW 0x0`		`dbf` `RW 0x0`	`pm` `RW 0x0`	`daif` `RW 0x0`	`hmc` `RO 0x0`	`huc` `RO 0x0`	`pr` `RW 0x0`

gmacgrp_mac_frame_filter Fields

Bit

Name

Description

Access

Reset

ra

Receive All

When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. 

When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

30:22

reserved_30_22

Reserved

RO

0x0

dntu

Drop non-TCP/UDP over IP Frames

When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. 

When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames.

Value	Description
0x0	NODROP
0x1	DROP

RW

0x0

ipfe

Layer 3 and Layer 4 Filter Enable

When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect.

When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields.

Value	Description
0x0	NODROP
0x1	DROP

RW

0x0

19:17

reserved_19_17

Reserved

RO

0x0

vtfe

VLAN Tag Filter Enable

When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. 

When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag.

Value	Description
0x0	NODROP
0x1	DROP

RW

0x0

15:11

reserved_15_11

Reserved

RO

0x0

hpf

Hash or Perfect Filter

When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. 

When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter.

Value	Description
0x0	DISABLED
0x1	ENABLED

RO

0x0

saf

Source Address Filter Enable

When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame.
When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.

Note: According to the IEEE specification, Bit 47 of the SA is reserved and set to 0. However, in DWC_gmac, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

saif

SA Inverse Filtering

When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. 

When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

7:6

pcf

Pass Control Frames

These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames).

00: MAC filters all control frames from reaching the application.
01: MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.
10: MAC forwards all control frames to application even if they fail the Address Filter.
11: MAC forwards control frames that pass the Address Filter.

The following conditions should be true for the PAUSE control frames processing:

Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1.
Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set.
Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.

Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is false, the PAUSE frames are considered as generic control frames. Therefore, to pass all control frames (including PAUSE control frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application).

Value	Description
0x0	MACFLTALLCFR
0x1	MACFWDXPAUSE
0x2	MACFWDFAIL
0x3	MACFWDPASS

RW

0x0

dbf

Disable Broadcast Frames

When this bit is set, the AFM module filters all incoming broadcast frames. In addition, it overrides all other filter settings. 

When this bit is reset, the AFM module passes all received broadcast frames.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

pm

Pass All Multicast

When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. 

When reset, filtering of multicast frame depends on HMC bit.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

daif

DA Inverse Filtering

When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.

When reset, normal filtering of frames is performed.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

hmc

Hash Multicast

When set, MAC performs destination address filtering of received multicast frames according to the hash table.

When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers.

Value	Description
0x0	DISABLED
0x1	ENABLED

RO

0x0

huc

Hash Unicast

When set, MAC performs destination address filtering of unicast frames according to the hash table.

When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers.

Value	Description
0x0	DISABLED
0x1	ENABLED

RO

0x0

pr

Promiscuous Mode

When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0