gmacgrp_wdog_timeout

          Register 55 (Watchdog Timeout Register) 
              This register controls the watchdog timeout for received frames.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF8000DC
i_emac_emac1 0xFF802000 0xFF8020DC
i_emac_emac2 0xFF804000 0xFF8040DC

Offset: 0xDC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_17

RO 0x0

pwe

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_14

RO 0x0

wto

RW 0x0

gmacgrp_wdog_timeout Fields

Bit Name Description Access Reset
31:17 reserved_31_17 
Reserved
 RO 0x0
16 pwe 
Programmable Watchdog Enable
                
                When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame.
                When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register).
RW 0x0
15:14 reserved_15_14 
Reserved
 RO 0x0
13:0 wto 
Watchdog Timeout
                
                When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame.
                
                Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped.
RW 0x0