gmacgrp_mmc_transmit_interrupt
Register 66 (MMC Transmit Interrupt Register)
The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_emac_emac0 | 0xFF800000 | 0xFF800108 |
| i_emac_emac1 | 0xFF802000 | 0xFF802108 |
| i_emac_emac2 | 0xFF804000 | 0xFF804108 |
Offset: 0x108
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
reserved_31_26 RO 0x0 |
txosizegfis RO 0x0 |
txvlangfis RO 0x0 |
txpausfis RO 0x0 |
txexdeffis RO 0x0 |
txgfrmis RO 0x0 |
txgoctis RO 0x0 |
txcarerfis RO 0x0 |
txexcolfis RO 0x0 |
txlatcolfis RO 0x0 |
txdeffis RO 0x0 |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
txmcolgfis RO 0x0 |
txscolgfis RO 0x0 |
txuflowerfis RO 0x0 |
txbcgbfis RO 0x0 |
txmcgbfis RO 0x0 |
txucgbfis RO 0x0 |
tx1024tmaxoctgbfis RO 0x0 |
tx512t1023octgbfis RO 0x0 |
tx256t511octgbfis RO 0x0 |
tx128t255octgbfis RO 0x0 |
tx65t127octgbfis RO 0x0 |
tx64octgbfis RO 0x0 |
txmcgfis RO 0x0 |
txbcgfis RO 0x0 |
txgbfrmis RO 0x0 |
txgboctis RO 0x0 |
gmacgrp_mmc_transmit_interrupt Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:26 | reserved_31_26 | Reserved |
RO | 0x0 | ||||||
| 25 | txosizegfis | MMC Transmit Oversize Good Frame Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. |
RO | 0x0 | ||||||
| 24 | txvlangfis | MMC Transmit VLAN Good Frame Counter Interrupt Status This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 23 | txpausfis | MMC Transmit Pause Frame Counter Interrupt Status This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 22 | txexdeffis | MMC Transmit Excessive Deferral Frame Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 21 | txgfrmis | MMC Transmit Good Frame Counter Interrupt Status This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 20 | txgoctis | MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 19 | txcarerfis | MMC Transmit Carrier Error Frame Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 18 | txexcolfis | MMC Transmit Excessive Collision Frame Counter Interrupt Status This bit is set when the txexcesscol counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 17 | txlatcolfis | MMC Transmit Late Collision Frame Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 16 | txdeffis | MMC Transmit Deferred Frame Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 15 | txmcolgfis | MMC Transmit Multiple Collision Good Frame Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 14 | txscolgfis | MMC Transmit Single Collision Good Frame Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 13 | txuflowerfis | MMC Transmit Underflow Error Frame Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 12 | txbcgbfis | MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 11 | txmcgbfis | MMC Transmit Multicast Good Bad Frame Counter Interrupt Status This bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 10 | txucgbfis | MMC Transmit Unicast Good Bad Frame Counter Interrupt Status This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 9 | tx1024tmaxoctgbfis | MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 8 | tx512t1023octgbfis | MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 7 | tx256t511octgbfis | MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 6 | tx128t255octgbfis | MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 5 | tx65t127octgbfis | MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 4 | tx64octgbfis | MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 3 | txmcgfis | MMC Transmit Multicast Good Frame Counter Interrupt Status This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 2 | txbcgfis | MMC Transmit Broadcast Good Frame Counter Interrupt Status This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 1 | txgbfrmis | MMC Transmit Good Bad Frame Counter Interrupt Status This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 0 | txgboctis | MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 |