dmagrp_hw_feature
Register 22 (HW Feature Register)
This register indicates the presence of the optional features or functions of the DWC_gmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_emac_emac0 | 0xFF800000 | 0xFF801058 |
| i_emac_emac1 | 0xFF802000 | 0xFF803058 |
| i_emac_emac2 | 0xFF804000 | 0xFF805058 |
Offset: 0x1058
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
reserved_31 RO 0x0 |
actphyif RO 0x0 |
savlanins RO 0x1 |
flexippsen RO 0x1 |
inttsen RO 0x1 |
enhdessel RO 0x1 |
txchcnt RO 0x0 |
rxchcnt RO 0x0 |
rxfifosize RO 0x1 |
rxtyp2coe RO 0x1 |
rxtyp1coe RO 0x0 |
txoesel RO 0x1 |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
avsel RO 0x1 |
eeesel RO 0x1 |
tsver2sel RO 0x1 |
tsver1sel RO 0x0 |
mmcsel RO 0x1 |
mgksel RO 0x0 |
rwksel RO 0x0 |
smasel RO 0x1 |
l3l4fltren RO 0x1 |
pcssel RO 0x0 |
addmacadrsel RO 0x1 |
hashsel RO 0x1 |
exthashen RO 0x1 |
hdsel RO 0x1 |
gmiisel RO 0x1 |
miisel RO 0x1 |
dmagrp_hw_feature Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | reserved_31 | Reserved |
RO | 0x0 | ||||||||||||||||||
| 30:28 | actphyif | Active or Selected PHY interface When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion * 0000: GMII or MII * 0001: RGMII * 0010: SGMII * 0011: TBI * 0100: RMII * 0101: RTBI * 0110: SMII * 0111: RevMII * All Others: Reserved
|
RO | 0x0 | ||||||||||||||||||
| 27 | savlanins | Source Address or VLAN Insertion |
RO | 0x1 | ||||||||||||||||||
| 26 | flexippsen | Flexible Pulse-Per-Second Output |
RO | 0x1 | ||||||||||||||||||
| 25 | inttsen | Timestamping with Internal System Time |
RO | 0x1 | ||||||||||||||||||
| 24 | enhdessel | Alternate (Enhanced Descriptor)
|
RO | 0x1 | ||||||||||||||||||
| 23:22 | txchcnt | Number of additional Tx channels
|
RO | 0x0 | ||||||||||||||||||
| 21:20 | rxchcnt | Number of additional Rx channels
|
RO | 0x0 | ||||||||||||||||||
| 19 | rxfifosize | Rx FIFO > 2,048 Bytes
|
RO | 0x1 | ||||||||||||||||||
| 18 | rxtyp2coe | IP Checksum Offload (Type 2) in Rx
|
RO | 0x1 | ||||||||||||||||||
| 17 | rxtyp1coe | IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE =1.
|
RO | 0x0 | ||||||||||||||||||
| 16 | txoesel | Checksum Offload in Tx
|
RO | 0x1 | ||||||||||||||||||
| 15 | avsel | AV Feature
|
RO | 0x1 | ||||||||||||||||||
| 14 | eeesel | Energy Efficient Ethernet
|
RO | 0x1 | ||||||||||||||||||
| 13 | tsver2sel | IEEE 1588-2008 Advanced Timestamp
|
RO | 0x1 | ||||||||||||||||||
| 12 | tsver1sel | Only IEEE 1588-2002 Timestamp
|
RO | 0x0 | ||||||||||||||||||
| 11 | mmcsel | RMON Module
|
RO | 0x1 | ||||||||||||||||||
| 10 | mgksel | PMT Magic Packet
|
RO | 0x0 | ||||||||||||||||||
| 9 | rwksel | PMT Remote Wakeup
|
RO | 0x0 | ||||||||||||||||||
| 8 | smasel | SMA (MDIO) Interface
|
RO | 0x1 | ||||||||||||||||||
| 7 | l3l4fltren | Layer 3 and Layer 4 Filter Feature |
RO | 0x1 | ||||||||||||||||||
| 6 | pcssel | PCS registers (TBI, SGMII, or RTBI PHY interface)
|
RO | 0x0 | ||||||||||||||||||
| 5 | addmacadrsel | Multiple MAC Address Registers
|
RO | 0x1 | ||||||||||||||||||
| 4 | hashsel | HASH Filter
|
RO | 0x1 | ||||||||||||||||||
| 3 | exthashen | Expanded DA Hash Filter |
RO | 0x1 | ||||||||||||||||||
| 2 | hdsel | Half-Duplex support
|
RO | 0x1 | ||||||||||||||||||
| 1 | gmiisel | 1000 Mbps support
|
RO | 0x1 | ||||||||||||||||||
| 0 | miisel | 10 or 100 Mbps support
|
RO | 0x1 |