gmacgrp_l3_l4_control3

         This register controls the operations of the filter 0 of Layer 3 and Layer 4.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800490
i_emac_emac1 0xFF802000 0xFF802490
i_emac_emac2 0xFF804000 0xFF804490

Offset: 0x490

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

l4dpim3

RW 0x0

l4dpm3

RW 0x0

l4spim3

RW 0x0

l4spm3

RW 0x0

Reserved

l4pen3

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

l3hdbm3

RW 0x0

l3hsbm3

RW 0x0

l3daim3

RW 0x0

l3dam3

RW 0x0

l3saim3

RW 0x0

l3sam3

RW 0x0

Reserved

l3pen3

RW 0x0

gmacgrp_l3_l4_control3 Fields

Bit Name Description Access Reset
21 l4dpim3 
When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching.
This bit is valid and applicable only when Bit 20 (L4DPM3) is set high.
RW 0x0
20 l4dpm3 
When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching.
 RW 0x0
19 l4spim3 
When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching.

This bit is valid and applicable only when Bit 18 (L4SPM3) is set high.
RW 0x0
18 l4spm3 
When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching.
 RW 0x0
16 l4pen3 
When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching.
The Layer 4 matching is done only when either L4SPM3 or L4DPM3 bit is set high.
RW 0x0
15:11 l3hdbm3 
Layer 3 IP DA Higher Bits Match
IPv4 Frames: 

This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field:
 * 0: No bits are masked.
 * 1: LSb[0] is masked.
 * 2: Two LSbs [1:0] are masked.
 * ...
 * 31: All bits except MSb are masked.

IPv6 Frames: 

Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM3, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM3[1:0] and L3HSBM3 bits:
 * 0: No bits are masked.
 * 1: LSb[0] is masked.
 * 2: Two LSbs [1:0] are masked.
 * ...
 * 127: All bits except MSb are masked.
This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.
 RW 0x0
10:6 l3hsbm3 
IPv4 Frames: 

This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field:
 * 0: No bits are masked.
 * 1: LSb[0] is masked.
 * 2: Two LSbs [1:0] are masked.
 * ...
 * 31: All bits except MSb are masked.

IPv6 Frames: 

This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames.
This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.
 RW 0x0
5 l3daim3 
When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching.

This bit is valid and applicable only when Bit 4 (L3DAM3) is set high.
 RW 0x0
4 l3dam3 
When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching.

Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 2 (L3SAM3) because either IPv6 DA or SA can be checked for filtering.
 RW 0x0
3 l3saim3 
When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching.

This bit is valid and applicable only when Bit 2 (L3SAM3) is set high.
 RW 0x0
2 l3sam3 
When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching.

Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 4 (L3DAM3) because either IPv6 SA or DA can be checked for filtering.
 RW 0x0
0 l3pen3 
When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames.
The Layer 3 matching is done only when either L3SAM3 or L3DAM3 bit is set high.
 RW 0x0