dmagrp_bus_mode

          Register 0 (Bus Mode Register) 

The Bus Mode register establishes the bus operating modes for the DMA.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF801000
i_emac_emac1 0xFF802000 0xFF803000
i_emac_emac2 0xFF804000 0xFF805000

Offset: 0x1000

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_26

RO 0x0

aal

RW 0x0

eightxpbl

RW 0x0

usp

RW 0x0

rpbl

RW 0x1

fb

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_14

RO 0x0

pbl

RW 0x1

atds

RW 0x0

dsl

RW 0x0

reserved_1

RO 0x0

swr

RW 0x1

dmagrp_bus_mode Fields

Bit Name Description Access Reset
30:26 reserved_30_26 
Reserved
 RO 0x0
25 aal 
Address Aligned Beats

When this bit is set high and the FB bit is equal to 1, the AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
24 eightxpbl 
PBLx8 Mode

When set high, this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
23 usp 
Use Seperate PBL

When set high, this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations.

When reset to low, the PBL value in Bits[13:8] is applicable for both DMA engines.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
22:17 rpbl 
Rx DMA PBL

This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.

The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior.
This field is valid and applicable only when USP is set high.
Value Description
0x1 RXDMAPBL1
0x2 RXDMAPBL2
0x4 RXDMAPBL4
0x8 RXDMAPBL8
0x10 RXDMAPBL6
0x20 RXDMAPBL32
RW 0x1
16 fb 
Fixed Burst

This bit controls whether the AXI Master interface performs fixed burst transfers or not. When set, the interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations.

For more information, see Bit 0 (UNDEF).
Value Description
0x0 NONFB
0x1 FB1_4_8_16
RW 0x0
15:14 reserved_15_14 
Reserved
 RW 0x0
13:8 pbl

Programmable Burst Length

These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions.

If the number of beats to be transferred is more than 32, then perform the following steps:

  1. Set the PBLx8 mode. <br>
  2. Set the PBL. <br>

For example, if the maximum number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL to 8. The PBL values have the following limitation: The maximum number of possible beats (PBL) is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified.

For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following list. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered.

Note: Note: In the half-duplex mode, the valid PBL range specified in the following list is applicable only for Tx FIFO.
  • 32-Bit Data Bus Width
    • 128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 16 or less. In the half-duplex mode, the valid PBL range is 8 or less for the 10 or 100 Mbps mode.
    • 256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 32 or less.
    • 512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 64 or less.
    • 1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 128 or less. In the half-duplex mode, the valid PBL range is 128 or less in the 10 or 100 Mbps mode and 64 or less in the 1000 Mbps mode.
    • 2 KB and Higher FIFO Depth: All PBL values are supported in the full-duplex mode and half-duplex modes.
RW 0x1
7 atds 
Alternate Descriptor Size
This bit is valid (read or write with default value of 0) when you select the Alternate Descriptor feature and any (or both) of the following features:
  • Advanced Timestamp
  • IPC Full Checksum Offload Engine (Type 2)

When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS). The software application must set this bit when timestamping is enabled in Register 448 (Timestamp Control Register) or Checksum Offload is enabled in Register 0 (MAC Configuration Register). This is required when the Advanced Timestamp feature or the IPC Full Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2) features are not enabled. In such cases, you can use the 16 bytes descriptor to save 4 bytes of memory.

When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). This bit preserves the backward compatibility for the descriptor size. In versions prior to 3.50a, the descriptor size is 16 bytes for both normal and enhanced descriptor. In version 3.50a, descriptor size is increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features.

Value Description
0x0 CLEARRST
0x1 RESET
RW 0x0
6:2 dsl 
Descriptor Skip Length

This bit specifies the number of Words to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode.
 RW 0x0
1 reserved_1 
Reserved_1
 RW 0x0
0 swr 
Software Reset

When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation has completed in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit .

 Note: <br>
 * The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function.
 * The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion.
Value Description
0x0 CLEARRST
0x1 RESET
RW 0x1