gmacgrp_genpio

          Register 56 (General Purpose IO Register) 
              This register provides the control to drive up to 4 bits of output ports (GPO) and the status of up to 4 input
              ports (GPIS). It also provides the control to generate interrupts on events occurring on the gpi_i pin.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF8000E0
i_emac_emac1 0xFF802000 0xFF8020E0
i_emac_emac2 0xFF804000 0xFF8040E0

Offset: 0xE0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_x

RO 0x0

gpit

RW 0x0

reserved_23_x

RO 0x0

gpie

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_x

RO 0x0

gpo

RW 0x0

reserved_7_x

RO 0x0

gpis

RO 0x0

gmacgrp_genpio Fields

Bit Name Description Access Reset
31:25 reserved_31_x 
Reserved
 RO 0x0
24 gpit 
GPI Type
                
                When set, this bit indicates that the corresponding GPIS is of latched-low (LL) type. When reset, this bit indicates that the corresponding GPIS is of latched-high (LH) type.
                The number of bits available in this field depend on the GP Input Signal Width option. Other bits are not used (reserved and always reset).
RW 0x0
23:17 reserved_23_x 
Reserved
 RO 0x0
16 gpie 
GPI Interrupt Enable
                
                When this bit is set and the programmed event (LL or LH) occurs on the corresponding GPIS bit, Bit 11 (GPIIS) of Register 14 (Interrupt Status Register) is set. Accordingly, the interrupt is generated on the mci_intr_o or sbd_intr_o. The GPIIS bit is cleared when the host reads the Bits[7:0] of this register.
                When reset, Bit 11 (GPIIS) of Register 14 (Interrupt Status Register) is not set when any event occurs on the corresponding GPIS bits.
                The number of bits available in this field depend on the GP Input Signal Width option. Other bits are not used (reserved and always reset).
 RW 0x0
15:9 reserved_15_x 
Reserved
 RO 0x0
8 gpo 
General Purpose Output
                
                When this bit is set, it directly drives the gpo_o output ports. When this bit is reset, it does not directly drive the gpo_o output ports.
                The number of bits available in this field depend on the GP Output Signal Width option. Other bits are not used (reserved and always reset).
RW 0x0
7:1 reserved_7_x 
Reserved
 RO 0x0
0 gpis 
General Purpose Input Status
                
                This field gives the status of the signals connected to the gpi_i input ports. This field is of the following types based on the setting of the corresponding GPIT field of this register:
                
                * Latched-low (LL): This field is cleared when the corresponding gpi_i input becomes low. This field remains low until the host reads this field. After this, this field reflects the current value of the gpi_i input. 
                * Latched-high (LH): This field is set when the corresponding gpi_i input becomes high. This field remains high until the host reads this field. After this, this field reflects the current value of the gpi_i input.
                <br>
                The number of bits available in this field depend on the GP Input Signal Width option. Other bits are not used (reserved and always reset).
RO 0x0