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1. Overview of the Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs
7. Core Clock Network in Agilex™ 3 FPGAs and SoCs
8. I/O PLLs in Agilex™ 3 FPGAs and SoCs
9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs
11. Hard Processor System in Agilex™ 3 SoCs
12. Transceivers in Agilex™ 3 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs
18. Device Security for Agilex™ 3 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs
20. Power Management for Agilex™ 3 FPGAs and SoCs
21. Software and Tools for Agilex™ 3 FPGAs and SoCs
22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview
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3. Second Generation Hyperflex® Core Architecture
The Agilex™ 3 FPGAs and SoCs are based on a core fabric featuring the second generation Hyperflex® core architecture.
| Advantage | Description |
|---|---|
| Higher throughput | Delivers, on average, 1.9x higher core clock frequency performance in designs from previous generation FPGAs to obtain throughput breakthroughs. |
| Improved power efficiency | Uses reduced IP size to consolidate designs that previously spanned multiple devices into a single device. |
| Greater design functionality | Uses faster clock frequency to reduce bus widths and reduce IP size. The reduced bus widths and IP size free up additional FPGA resources to add greater functionality. |
| Increased designer productivity | Boosts performance with less routing congestion and fewer design iterations using the Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure. |
Additional to traditional ALM user registers, the Hyperflex® core architecture adds bypassable registers called Hyper-Registers:
- Distributed throughout the FPGA fabric.
- Available on every interconnect routing segment and at the inputs of all functional blocks.
Figure 4. Bypassable Hyper-Register
In the second generation Hyperflex® core architecture, Altera optimized the number of registers to improve timing closure time and fabric area utilization.
Figure 5. Hyperflex® Core Architecture
The Hyper-Registers enable you to achieve core performance increases using key design techniques. If you implement these design techniques, the Hyper-Aware design tools automatically utilizes the Hyper-Registers to achieve maximum core clock frequency:
- Fine grain Hyper-Retiming to eliminate critical paths
- Zero-latency Hyper-Pipelining to eliminate routing delays
- Flexible Hyper-Optimization for best-in-class performance