Agilex™ 3 FPGAs and SoCs Device Overview

ID 817231
Date 9/23/2024
Public
Document Table of Contents

15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs

Configuration via protocol (CvP) using PCIe* allows you to configure the Agilex™ 3 FPGAs and SoCs across the PCIe* bus. This capability simplifies board layout and increases system integration.

The embedded PCIe* hard IP operates in autonomous mode before the FPGA is configured. Using this hard IP, you can power up and activate the PCIe* bus within the 100 ms time allowed by the PCIe* specification.

The Agilex™ 3 FPGAs and SoCs also support partial reconfiguration across the PCIe* bus. This capability reduces system downtime by keeping the PCIe* link active during device reconfiguration.