Agilex™ 3 FPGAs and SoCs Device Overview

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ID 817231
Date 9/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 3 FPGAs and SoCs 2. Agilex™ 3 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs 7. Core Clock Network in Agilex™ 3 FPGAs and SoCs 8. I/O PLLs in Agilex™ 3 FPGAs and SoCs 9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs 10. External Memory Interface in Agilex™ 3 FPGAs and SoCs 11. Hard Processor System in Agilex™ 3 SoCs 12. Transceivers in Agilex™ 3 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs 18. Device Security for Agilex™ 3 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs 20. Power Management for Agilex™ 3 FPGAs and SoCs 21. Software and Tools for Agilex™ 3 FPGAs and SoCs 22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 3 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 3 FPGAs and SoCs 1.2. Agilex™ 3 FPGAs and SoCs Block Diagram 1.3. Agilex™ 3 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 3 SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan x
2.1. Agilex™ 3 FPGAs and SoCs C-Series 2.2. Agilex™ 3 FPGAs and SoCs C-Series Package Options 2.3. Part Number Decoder
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 3 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 3 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 3 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 3 FPGAs and SoCs
1. Overview of the Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs
7. Core Clock Network in Agilex™ 3 FPGAs and SoCs
8. I/O PLLs in Agilex™ 3 FPGAs and SoCs
9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs
11. Hard Processor System in Agilex™ 3 SoCs
12. Transceivers in Agilex™ 3 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs
18. Device Security for Agilex™ 3 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs
20. Power Management for Agilex™ 3 FPGAs and SoCs
21. Software and Tools for Agilex™ 3 FPGAs and SoCs
22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview

18. Device Security for Agilex™ 3 FPGAs and SoCs

Agilex™ 3 FPGAs and SoCs are built with robust security features and managed by the SDM. The devices prioritize the operations of the SDM over fabric and other microprocessor tasks.

The dedicated SDM manages and supports the following critical security features:

  • Manages FPGA configuration process and all security features
  • Performs authenticated FPGA configuration and HPS boot
  • Supports FPGA bitstream encryption, secure key provisioning, and PUF key storage
  • Supports platform attestation using the SPDM protocol
  • Manages runtime sensors and supports active tamper detection and responses
  • Provides access to hardened cryptographic engines as a service

In addition to the preceding list, the following table summarizes the three pillars of security with the advanced security features that Agilex™ 3 FPGAs and SoCs support.

Table 21.   Agilex™ 3 FPGAs and SoCs Advanced Security Features
Pillar of Security Device Security Features
Confidentiality, integrity, and availability
  • Encryption
  • Authentication
  • Attestation
  • Secure boot
  • User access to cryptographic functions
  • Secure debug
  • Vendor authorized boot
Key protection
  • Side channel mitigation
  • Physical anti-tamper detection and response
Secure manufacturing
  • Black key provisioning
  • Secure returned merchandise authorization (RMA)
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