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1. Overview of the Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs
7. Core Clock Network in Agilex™ 3 FPGAs and SoCs
8. I/O PLLs in Agilex™ 3 FPGAs and SoCs
9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs
11. Hard Processor System in Agilex™ 3 SoCs
12. Transceivers in Agilex™ 3 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs
18. Device Security for Agilex™ 3 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs
20. Power Management for Agilex™ 3 FPGAs and SoCs
21. Software and Tools for Agilex™ 3 FPGAs and SoCs
22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview
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4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs
The Agilex™ 3 FPGAs and SoCs use an enhanced adaptive logic module (ALM) as shown in the ALM Block Diagram figure and its key features and capabilities are listed in the Key Features and Capabilities of the ALM table.
Figure 6. ALM Block DiagramThis figure shows the ALM with 8-input fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.
| Key Feature | Capability |
|---|---|
| High register count | Together with the second generation Hyperflex® architecture, the four registers per 8-input fracturable LUT enables maximized core performance at very high core logic utilization. |
| ALM operating modes | Optimize core logic utilization by implementing an extended 7-input logic function, a single 6-input logic function, or two smaller independent functions (for example, two 4-input functions). |
| Two clock sources | Two clock sources per ALM generate two normal clocks and two delayed clocks to drive the ALM registers, resulting in more clock domains and time-borrowing capability. |
| Additional LUT outputs | Additional fast 6-LUT and 5-LUT outputs for combinatorial functions improve critical path for logic cascade. |
| Improved register packing | The improved register packing, including 5-input LUT with two packed register paths, results in more efficient usage of the fabric area and improved critical path. |
| Latch mode support | The ALM supports latch mode in the address latch enable. |
The Quartus® Prime software capitalizes on the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Quartus® Prime software simplifies design reuse as the software automatically maps legacy designs into the ALM architecture of the Agilex™ 3 FPGAs and SoCs.