| Packaging |
- Multiple devices with identical package footprints allows seamless migration across different device densities
- Variable Pitch BGA (VPBGA) package3 for smaller package form factor and to help reduce the number of PCB layers
- 0.5 mm ball pitch package option for small form-factor with more I/O counts
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| High performance core fabric |
- Second Generation Hyperflex® core architecture with Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks
- Enhanced adaptive logic module (ALM)
- Improved multi-track routing architecture reduces congestion and improves compile times
- Hierarchical core clocking architecture with programmable clock tree synthesis
- Fine-grained partial reconfiguration
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| Internal memory blocks |
- Multi-level on-chip memory hierarchy
- M20K—20 kilobits with hard error correction code (ECC) support
- MLAB—640-bit distributed LUTRAM
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| Variable precision DSP blocks |
- Variable precision DSP blocks with hard IEEE 754-compliant floating-point units, including support for:
- Single-precision FP32 (32-bit arithmetic)
- Half-precision FP16 (16-bit arithmetic) and FP19 (19-bit arithmetic) floating point modes
- Tensor floating point FP19 floating point modes
- BFLOAT16 floating-point format
- High-performance AI Tensor blocks:
- Enables high-performance compute density of FPGA fabric Tera Operations Per Second (TOPS)
- Up to 2.54 INT8 TOPS for AI workloads
- Hardware programmable for AI with customized workloads
- Supports push-button flow from industry standard frameworks, such as TensorFlow* , to FPGA bitstream
- Every DSP block supports INT16 complex multiplication mode
- Supports signal processing with precision ranging from 9×9 up to 54×54
- Native 27×27, 18×19, and 9×9 multiplication modes
- 64-bit accumulator and cascade for systolic 200 GbE finite impulse responses (FIRs)
- Internal coefficient memory banks
- Pre-adder/subtractor improves efficiency
- 2× additional pipeline register increases performance and reduces power consumption
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| Core clock networks |
- Programmable clock tree synthesis—backwards compatible with global, regional and peripheral clock networks
- Synthesize clocks where needed only—minimizes dynamic power
- 625 MHz LVDS interface clocking—supports 1,250 Mbps LVDS interface through the 1.3 V TDS standard compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
- 1,067 MHz external memory interface clocking, supports 2,133 Mbps LPDDR4 interface
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| General purpose I/Os |
General |
- 1.25 Gbps 1.3 V TDS standard compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
- 1.0 V, 1.05 V, 1.1 V, and 1.2 V single-ended LVCMOS interfacing
- 1.8 V, 2.5 V, and 3.3 V single-ended LVCMOS/LVTTL I/O
- On-chip termination (OCT)
- Over 500 total GPIOs available
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| External memory interface (Hard IP) |
1,067 MHz (2,133 Mbps) LPDDR4 external memory interface |
| MIPI* |
MIPI* D-PHY* v2.5 at up to 2.5 Gbps 4 per lane |
| Phase locked loops (PLL) |
I/O PLL |
- Integer PLLs adjacent to general purpose I/Os
- Precision frequency synthesis
- Clock delay compensation
- Zero-delay buffering
- Support external memory and LVDS-compatible interface
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| Transmit PLLs (TX PLLs) |
- Precise fractional synthesis
- Ultra low jitter with LC tank-based PLL
- Supports transceiver interfaces
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| System PLL |
- One System PLL per GTS transceiver bank
- Integer mode
- Precision frequency synthesis
- Supports transceiver-to-fabric interface
- You can repurpose the System PLL for core usage if it is not used by the GTS transceiver
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| Memory controller support |
Multiple hard IP instantiations in each device
- LPDDR4 hard memory controller
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| Transceivers |
PCIe* |
PCIe* rates up to PCIe* 3.0, 8 Gbps NRZ |
| Networking |
- Insertion loss compliant to 802.3bj and CEI 25G-LR standards
- Oversampling capability for data rates below 1 Gbps
- SFP+ optical module support
- Adaptive linear and decision feedback equalization
- Transmit pre-emphasis and de-emphasis
- Dynamic reconfiguration of individual GTS transceiver channels
- On-chip instrumentation ( Quartus® Prime Eye Viewer with non-destructive eye height and destructive eye width margining)
- Continuous operating range of 1 Gbps to 12.5 Gbps NRZ
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| Transceiver hard IP |
PCIe* |
- One hard IP instantiations in each device
- TLP bypass feature
- Single-root I/O virtualization (SR-IOV)
- Precise time management
- Up to PCIe* 3.0 ×4 EP and RP
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| Other protocols |
- CR/KR (AN/LT)
- 1588 PTP
- MAC, PCS, and FEC bypass options
- Ethernet IP configuration: 4 × 10 GbE MAC, PCS, and FEC
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| Configuration |
- Dedicated SDM
- Software-programmable device configuration
- Serial flash interface
- Configuration from parallel flash through external host
- Fine-grained partial reconfiguration of core fabric—add or remove system logic while the device is operating
- Dynamic reconfiguration of GTS transceivers and PLLs
- Comprehensive set of security features including AES-256, SHA-256/384, and ECDSA-256/384 accelerators
- PUF service
- Platform attestation
- Anti-tamper features
- Configuration via protocol (CvP) using PCIe* 1.0, 2.0, or 3.0
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| Functional safety |
- Functional Safety Data Package (FSDP)
- Improved FPGA diagnostic measures enable use of Agilex™ 3 FPGAs in safety-critical applications
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| Software and tools |
- Quartus® Prime Pro Edition design suite with new compiler and Hyper-Aware design flow
- New compile innovations in each Intel® oneAPI release
- Transceiver toolkit
- Platform Designer IP integration tool
- Altera DSP Builder for Intel® FPGAs advanced blockset
- Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA)
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