Agilex™ 3 FPGAs and SoCs Device Overview

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ID 817231
Date 9/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 3 FPGAs and SoCs 2. Agilex™ 3 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs 7. Core Clock Network in Agilex™ 3 FPGAs and SoCs 8. I/O PLLs in Agilex™ 3 FPGAs and SoCs 9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs 10. External Memory Interface in Agilex™ 3 FPGAs and SoCs 11. Hard Processor System in Agilex™ 3 SoCs 12. Transceivers in Agilex™ 3 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs 18. Device Security for Agilex™ 3 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs 20. Power Management for Agilex™ 3 FPGAs and SoCs 21. Software and Tools for Agilex™ 3 FPGAs and SoCs 22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 3 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 3 FPGAs and SoCs 1.2. Agilex™ 3 FPGAs and SoCs Block Diagram 1.3. Agilex™ 3 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 3 SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan x
2.1. Agilex™ 3 FPGAs and SoCs C-Series 2.2. Agilex™ 3 FPGAs and SoCs C-Series Package Options 2.3. Part Number Decoder
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 3 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 3 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 3 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 3 FPGAs and SoCs
1. Overview of the Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs
7. Core Clock Network in Agilex™ 3 FPGAs and SoCs
8. I/O PLLs in Agilex™ 3 FPGAs and SoCs
9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs
11. Hard Processor System in Agilex™ 3 SoCs
12. Transceivers in Agilex™ 3 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs
18. Device Security for Agilex™ 3 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs
20. Power Management for Agilex™ 3 FPGAs and SoCs
21. Software and Tools for Agilex™ 3 FPGAs and SoCs
22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview

2.1. Agilex™ 3 FPGAs and SoCs C-Series

Table 4.   C-Series FPGA Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device

Logic Element

 Adaptive Logic Module M20K

MLAB

 DSP
Count

Size (Mb)

 Count

Size (Mb)

 18×19 Multipliers

Peak INT8

(TOPS5 )

A3C025 25,075 8,500 65 1.27 450 0.27 68 0.47
A3C050 47,200 16,000 123 2.40 800 0.49 130 0.90
A3C065 65,490 22,200 169 3.30 1,050 0.64 179 1.21
A3C100 100,300 34,000 262 5.12 2,000 1.22 276 1.90
A3C135 135,110 45,800 353 6.89 2,300 1.40 368 2.54
Table 5.   C-Series FPGA Family Plan—I/Os and InterfacesThe values in this table are maximum resources or performance.
Device

HVIO

(1.8 V–3.3 V)

HSIO

(1.0 V–1.3 V)

PLL Count

1.3 V LVDS Pairs

at 1.25 Gbps

LPDDR4 Interface

(×32)

 MIPI*

D-PHY*

Interface
I/O PLL Fabric-Feeding I/O PLL6
A3C025 160 96 2 5 48 0 0
A3C050 160 96 2 5 48 1 7
A3C065 160 96 2 5 48 1 7
A3C100 200 192 4 8 96 2 14
A3C135 200 192 4 8 96 2 14
Table 6.   C-Series FPGA Family Plan—Transceivers and HPS

The values in this table are maximum resources or performance.
Device

PCIe* 3.0 ×4

HPS
Processor Cache Size
A3C025 — — —
A3C050 — — —
A3C065 — — —
A3C100 1
  • Dual core Arm* Cortex* -A55 up to 800 MHz
  • 2 MB L3
  • Cortex* -A55:
    • 32 KB L1
    • 128 KB L2
A3C135 1
5 Tera Operations Per Second
6 The fabric-feeding I/O PLL counts include the System PLL in the GTS transceiver banks. You can use the System PLL for core fabric usage if you do not use it for the transceiver.
Level Two Title