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1. Overview of the Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs
7. Core Clock Network in Agilex™ 3 FPGAs and SoCs
8. I/O PLLs in Agilex™ 3 FPGAs and SoCs
9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs
11. Hard Processor System in Agilex™ 3 SoCs
12. Transceivers in Agilex™ 3 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs
18. Device Security for Agilex™ 3 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs
20. Power Management for Agilex™ 3 FPGAs and SoCs
21. Software and Tools for Agilex™ 3 FPGAs and SoCs
22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview
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5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs
The embedded memory blocks in Agilex™ 3 FPGAs and SoCs are similar to the embedded memory of previous generation Altera FPGAs.
Feature | MLAB | M20K |
---|---|---|
Usage | For wide and shallow memory configurations | For supporting larger memory configurations |
Block size | 640 bits | 20 kilobits |
Configurations |
|
|
Hard ECC | — | Yes |
Modes | Single-port RAM, dual-port RAM, FIFO, ROM, and shift register |