Agilex™ 3 FPGAs and SoCs Device Overview

ID 817231
Date 9/23/2024
Public
Document Table of Contents

9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs

The Agilex™ 3 FPGAs and SoCs are equipped with two types of general purpose I/Os—the high-speed I/Os (HSIO) and the high-voltage I/Os (HVIO). Both HSIO and HVIO enable important support for edge applications in Agilex™ 3 FPGAs and SoCs.
Table 12.  I/O Standards Support and Performance
I/O Type I/Os Per Bank I/O Standard Specification Notes
HSIO 969 LVCMOS 1.0 V, 1.05 V, 1.1 V, and 1.2 V single-ended
TDS
  • 1.3 V
  • Up to 1.25 Gbps
Works with the LVDS SERDES Intel® FPGA IP
MIPI* D-PHY*
  • Version 2.5
  • Up to 2.5 Gbps10 (high speed and low power mode)

Supports up to eight data lanes:

  • 1D+C
  • 2D+C
  • 4D+C
  • 8D+C
SGMII (TDS) Up to 1.25 Gbps If required, add AC coupling
HVIO 20 LVCMOS/LVTTL
  • 1.8 V single-ended
  • 0.250 Gbps (125 MHz DDR)
RGMII support at 1.8 V
  • 2.5 V/3.3 V single-ended
  • 0.200 Gbps (100 MHz DDR)
9 There are two sub-banks in each HSIO bank. Each sub-bank is powered by its own VCCIO.
10 Up to 2.5 Gbps for long reference channel.