Agilex™ 3 FPGAs and SoCs Device Overview

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ID 817231
Date 9/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 3 FPGAs and SoCs 2. Agilex™ 3 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs 7. Core Clock Network in Agilex™ 3 FPGAs and SoCs 8. I/O PLLs in Agilex™ 3 FPGAs and SoCs 9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs 10. External Memory Interface in Agilex™ 3 FPGAs and SoCs 11. Hard Processor System in Agilex™ 3 SoCs 12. Transceivers in Agilex™ 3 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs 18. Device Security for Agilex™ 3 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs 20. Power Management for Agilex™ 3 FPGAs and SoCs 21. Software and Tools for Agilex™ 3 FPGAs and SoCs 22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 3 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 3 FPGAs and SoCs 1.2. Agilex™ 3 FPGAs and SoCs Block Diagram 1.3. Agilex™ 3 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 3 SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan x
2.1. Agilex™ 3 FPGAs and SoCs C-Series 2.2. Agilex™ 3 FPGAs and SoCs C-Series Package Options 2.3. Part Number Decoder
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 3 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 3 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 3 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 3 FPGAs and SoCs
1. Overview of the Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 3 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 3 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 3 FPGAs and SoCs
7. Core Clock Network in Agilex™ 3 FPGAs and SoCs
8. I/O PLLs in Agilex™ 3 FPGAs and SoCs
9. General Purpose I/Os in Agilex™ 3 FPGAs and SoCs
10. External Memory Interface in Agilex™ 3 FPGAs and SoCs
11. Hard Processor System in Agilex™ 3 SoCs
12. Transceivers in Agilex™ 3 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 3 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 3 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 3 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 3 FPGAs and SoCs
18. Device Security for Agilex™ 3 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs
20. Power Management for Agilex™ 3 FPGAs and SoCs
21. Software and Tools for Agilex™ 3 FPGAs and SoCs
22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview

16. Device Configuration and the SDM in Agilex™ 3 FPGAs and SoCs

All Agilex™ 3 FPGAs and SoCs contain an SDM. The SDM is a triple-redundant processor that serves as the point of entry into the device for all JTAG and configuration commands. Additionally, the SDM in the Agilex™ 3 FPGAs and SoCs enables system certification to FIPS140-3 layer 2 compliance.

The SDM bootstraps the HPS in Agilex™ 3 SoCs. This bootstrapping ensures that the HPS boots using the same security features available to the FPGA.

Figure 14. SDM Block Diagram

During configuration, the Agilex™ 3 FPGA or SoC divides into logical sectors. A local sector manager (LSM) manages each logical sector. The SDM passes configuration data to each LSMs across the on-chip configuration network.

Advantages of the sector-based approach:

  • Enables independent configuration of the sectors—one at a time or in parallel
  • Achieves simplified sector configuration and reconfiguration
  • Reduces overall configuration time caused by inherent parallelism.

The Agilex™ 3 FPGAs and SoCs use the same sector-based approach to respond to SEUs and security attacks.

Although the sectors provide a logical separation for device configuration and reconfiguration, the sectors overlay the normal rows and columns of FPGA logic and routing:

  • No impact to the Quartus® Prime software place and route
  • No impact to the timing of logic signals that cross the sector boundaries

The SDM enables robust, secure, and fully-authenticated device configuration. Additionally, the SDM allows you to customize the configuration scheme, enhancing device security.

Advantages of the SDM-based device configuration approach:

  • Provides a dedicated secure configuration manager
  • Reduces device configuration time because sectors are configured in parallel
  • Enables an updatable configuration process
  • Supports partial reconfiguration
  • Allows remote system update
  • Supports zeroization of whole device or individual sectors
Table 20.  Supported Configuration Schemes for Agilex™ 3 FPGAs
Configuration Scheme Data Width Maximum Data Rate
Active Serial (AS) normal and fast modes 4 bits 4 bits × 166 MHz = 664 Mbps
Avalon® streaming interface ×16 16 bits 16 bits × 125 MHz = 2 Gbps
Avalon® streaming interface ×8 8 bits 8 bits × 125 MHz = 1 Gbps
JTAG 1 bit 1 bit × 30 MHz = 30 Mbps
Configuration via Protocol (CvP) ×1, ×2, and ×4 lanes

The maximum data rate depends on the PCIe* generation and number of lanes. Typically, the data rate of the internal configuration data path of the device, instead of the width of the PCIe* link, limits the configuration data width.

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