GTS CPRI PHY Intel® FPGA IP User Guide

Download PDF
ID 814577
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY IP Troubleshooting 8. GTS CPRI PHY Intel FPGA IP User Guide Archives 9. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY IP Troubleshooting
8. GTS CPRI PHY Intel FPGA IP User Guide Archives
9. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

3. GTS CPRI PHY IP Parameter Settings

You customize the IP by specifying parameters in the IP parameter editor.
Figure 4. GTS CPRI PHY IP Parameter Editor
Table 7.  GTS CPRI PHY IP Parameter Settings: IP Tab
Parameter Supported Values Default Setting Description
CPRI General Options
CPRI Rate
  • 1.2288G (8b/10b)
  • 2.4576G (8b/10b)
  • 3.072G (8b/10b)
  • 4.9152G (8b/10b)
  • 6.144G (8b/10b)
  • 9.8304G (8b/10b)
  • 10.1376G (64b/66b)
  • 12.16512G (64b/66b)
  • 24.33024G (64b/66b)
 10.1376G (64b/66b) Selects the CPRI data rate.
  • Agilex 5 E-Series device group A and Agilex 5 D-Series devices support 24G and below
  • Agilex 5 E-Series device group B support 12G and below
  • Agilex 5 E-Series device group A and group B with device/tile revision R0 only support 10G and below
CPRI Core Options
System PLL Frequency 491.52 MHz or 805.664062 MHz 491.52 MHz Select the system PLL frequency for your IP.
  • Agilex 5 E-Series device group A and Agilex 5 D-Series devices support 805.664062 MHz
Enable CDR Clock Output
  • On
  • Off
 Off

Turn on this parameter to enable CDR reference clock output.

o_cdr_divclk= refclk/N

Refer to the Required Clock Frequencies for exact values.

CPRI PMA Options
PMA Reference Frequency
  • 153.6 MHz
  • 184.32 MHz
  • 122.88 MHz
 184.32 MHz Reference clock frequency support:
  • For CPRI line rates that include 8b/10b soft PCS, use a reference clock of 153.6 MHz or 122.88 MHz.
  • For CPRI line rates that include 64b/66b hard PCS, use a reference clock of 184.32 MHz or 122.88 MHz.
Configuration, Debug, and Extension Option

Enable Debug Endpoint for Datapath and PMA Avalon Memory-Mapped Interface

  • On
  • Off
 Off

When turned on, the GTS CPRI PHY Intel FPGA IP includes an embedded Debug Endpoint that internally connects the Avalon memory-mapped agent interface. The Debug Endpoint can access the reconfiguration space of the datapath and PMA interface block. It can perform certain tests and debug functions through the JTAG using the System Console. This option may require that you include a jtag_debug link in the system.


Section Content
Analog Parameters for GTS IPs

Related Information
Level Two Title