GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY IP Troubleshooting 8. GTS CPRI PHY Intel FPGA IP User Guide Archives 9. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY IP Troubleshooting
8. GTS CPRI PHY Intel FPGA IP User Guide Archives
9. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.2. GTS CPRI PHY IP Reset Signals

Each of the CPRI PHY channels in the IP has its own set of reset signals. The i_reconfig_reset port is shared.
Table 18.  Reset Signals
Port Name Width (Bits) Domain Description
i_tx_rst_n 1 Asynchronous Resets the selected TX datapath. Active low.
o_tx_rst_ack_n 1 Asynchronous TX datapath reset acknowledgement. Active low.
o_tx_ready 1 Asynchronous TX datapath is out of reset and ready.
i_rx_rst_n 1 Asynchronous Resets the selected RX datapath. Active low.
o_rx_rst_ack_n 1 Asynchronous RX datapath reset acknowledgement. Active low.
o_rx_ready 1 Asynchronous RX datapath is out of reset and ready.
i_reconfig_reset 1 i_reconfig_clk Reconfig reset. Resets the AVMM soft logics to the HIP and resets CPRI PHY soft CSR, but does not reset HIP CSRs. Active high. Must be asserted once upon power-up.
o_src_rs_req 1 i_reconfig_clk

Request signal from Soft Reset Controller (SRC) to GTS Reset Sequencer Intel FPGA IP for reset operation. Asserts when there is a request to toggle reset.

In case of reset group of more than one SRC_Lane, only Initiator SRC_Lane requests for access grant.
i_src_rs_grant 1 i_reconfig_clk

Grant signal from GTS Reset Sequencer Intel FPGA IP to SRC. Asserts when the reset request is granted by the Reset Sequencer Intel FPGA IP.

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