GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY IP Troubleshooting 8. GTS CPRI PHY Intel FPGA IP User Guide Archives 9. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY IP Troubleshooting
8. GTS CPRI PHY Intel FPGA IP User Guide Archives
9. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.6. GTS CPRI PHY IP TX Interface (8b/10b)

The TX 8b/10b interface is available only if you turn on Enable reconfiguration to 8b/10b datapath or if you select the 8b/10b CPRI line rate. For the CPRI PHY to power up in the 64b/66b line rate, the IP asserts these signals when you reconfigure the IP at runtime to enter the 8b/10b line rate.

Table 22.  GTS CPRI PHY IP TX 8b/10b Interface
Port Name Width (Bits) Domain Description
i_tx_d[15:0] 16 o_tx_clkout2 Indicates 8b/10b TX data for the corresponding CPRI PHY channel.
i_tx_c[1:0] 2 o_tx_clkout2 Indicates 8b/10b TX control for the corresponding CPRI PHY channel.
i_tx_d_x2 [31:0] 32 o_tx_clkout2 Indicates 8b/10b TX data for the corresponding 6G and 9.8G CPRI PHY channel.
i_tx_c_x2 [3:0] 4 o_tx_clkout2 Indicates 8b/10b TX control for the corresponding 6G and 9.8G CPRI PHY channel.
When you transmit the data using the TX 8b/10b interface:
  • The frames are 8b/10b encoded. Each byte in i_tx_d has a corresponding bit in i_tx_c that indicates whether the byte is a control byte or a data byte. For example, i_tx_c[1] is the control bit for i_tx_d[15:8].
  • The byte order for the TX interface flows from right to left and the first byte that the IP transmits is i_tx_d[7:0].
  • The first bit that the IP transmits is i_tx_d[0].
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