GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 8/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

3.1. Analog Parameters for GTS IPs

You can use the transceiver analog parameter settings to tune the analog functions in the GTS PMAs while designing high-speed serial protocol solutions. You can use this feature to compensate for signal losses for high data rate communications.

You can choose to set the transceiver Analog TX and Analog RX parameters in the Analog Parameters tab of the GTS Intel FPGA IP GUI. You can also set the HSSI_PARAMETER in the .qsf file for a specific lane that you have configured within the GTS IP Intel FPGA IP GUI instance. Setting these parameters via the .qsf file has precedence over the analog parameter settings in the IP GUI.

Figure 5. Analog Parameter Options in Parameter Editor
Table 8.  GTS Transmitter Analog Settings
Parameter Values Description
Spread Spectrum DISABLE or ENABLE Specifies whether TX PLL reference clock is spread spectrum. Default value is DISABLE.
Note: Spread spectrum is not supported when you use the fast PLL mode of the TX PLL. The operating range of the VCO for the fast PLL mode is 13.5 GHz to 16.0 GHz. Data rates in this range and those represented by division factors of 2, 4, 8, and 16 are all excluded from enabling spread spectrum.
Enable TX P&N Invert DISABLE or ENABLE Invert TX serial outputs P and N pins. Default value is DISABLE.
TX EQ Post Tap 1, 1.0 step size 0 to 19 TX equalization control for Post Tap 1. Default value is 5 .
TX EQ Main Tap, 1.0 step size 0 to 55 TX equalization control for Main Tap. Default value is 52.
TX EQ Pre Tap 1, 1.0 step size 0 to 15 TX equalization control for Pre Tap 1. Default value is 0.
TX EQ Pre Tap 2, 1.0 step size 0 to 7 TX equalization control for Pre Tap 2. Default value is 0.
Table 9.  Receiver Analog Settings
Parameter Values Description
RX Adaptation mode auto or manual Specifies the type of RX adaptation:
  • Auto adaptation — firmware based adaptation mode.
  • Manual adaptation — firmware based adaptation is disabled. You must configure and control the RX analog parameters such as RX EQ VGA Gain, RX EQ High Frequency Boost, and RX EQ DFE Tap 1 to tune the RX links in Analog Parameters tab of the IP GUI or in .qsf assignment file.

You can change the RX Adaptation mode to manual if you are running at a lower data rate. However, if you are running at a low data rate but the link is lossy, you may need to use the auto adaptation mode. Default value is auto.

Enable RX P&N Invert DISABLE or ENABLE Invert RX serial input P and N pins. Default value is DISABLE.

RX External Coupling Mode

AC or DC Specifies the type of external on-board coupling mode. Default value is AC.
Selects value of RX termination mode GROUNDED or DIFFERENTIAL Specifies the RX PMA buffer termination mode.

GROUNDED mode is used for AC coupled link.

DIFFERENTIAL mode is used for DC coupled link.

Default value is GROUNDED.
Selects value of RX onchip termination R_1(85 omhs)

R_2(100 omhs)

Selects RX on-chip termination resistor value. Default value is R_2(100 omhs).
RX EQ VGA Gain 0 to 63 Select the RX Equalization VGA Gain setting. Only available if you configure the RX Adaptation mode to manual. Not available when RX adaptation mode is set to auto. Default value is 0.
RX EQ High Frequency Boost 0 to 63 Select the RX Equalization High Frequency Boost setting. This option is only available if you configure the RX Adaptation mode to manual. Not available when RX adaptation mode is auto. Default value is 0.
RX EQ DFE Tap1 0 to 63 Select the RX Equalization DFE Tap1 setting. Only available if you configure the RX Adaptation mode to manual. Not available when RX adaptation mode is set to auto. Default value is 0.
1 The Spread Spectrum clocking mode is enabled by default when you select the Display Port protocol in the PMA Configuration Rules setting.
2 This is the default value but you can change this value in the Analog Parameter GUI or the HSSI_PARAMETER in the .qsf file.
3 Preliminary setting pending hardware verification.
Level Two Title