GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

2. GTS Serial Lite IV Intel® FPGA IP Overview

GTS Serial Lite IV Intel® FPGA IP is suitable for high bandwidth data communication for chip-to-chip, board-to-board, and backplane applications.

The GTS Serial Lite IV Intel® FPGA IP incorporates media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) blocks.

The IP supports data transfer speeds of:.
  • Up to 16 Gbps per lane with a maximum of 4 lane for NRZ mode GTS transceiver.

This IP offers high bandwidth, low overhead frames, low I/O count, and supports high scalability in both numbers of lanes and speed. This IP is also easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the transceiver.

This IP supports two transmission modes:
  • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
  • Full mode—This is a packet transfer mode. In this mode, the IP sends a burst and a sync cycle at the start and end of a packet as delimiters.
Figure 1.  GTS Serial Lite IV High Level Block Diagram

You can generate GTS Serial Lite IV Intel® FPGA IP design examples to learn more about the IP features.