GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

6.1. Clock Signals

Table 19.  Clock Signals
Name Width Direction Description
tx_core_clkout 1 Output TX core clock for the EFIFO, TX MAC and user logics in the TX datapath.

This clock is generated from the custom PCS block.

rx_core_clkout 1 Output RX core clock for the EFIFO, RX deskew FIFO, RX MAC and user logics in the RX datapath.

This clock is generated from the custom PCS block.

xcvr_ref_clk 1 Input Transceiver reference clock.

This clock must be connected to the transceiver bank local reference clock or regional reference clock pins.

xcvr_ref_clk_n 1 Input Transceiver reference clock.

This signal must be unconnected and unassigned in your design.

reconfig_clk 1 Input Input clock for PMA reconfiguration interface.

The clock frequency is 100 to 162 MHz.

Connect this input clock signal to external clock circuits or oscillators.

sys_clk 1 Input System PLL clock.

Connect this clock to the output signal (o_syspll_c0) of the GTS System PLL Clocks Intel FPGA IP.

pma_cu_clk 1 Input GTS reset sequencer clock.

Connect this clock to the output signal (o_pma_cu_clk) of the GTS Reset Sequencer Intel FPGA IP.