GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

6.2. Reset Signals

Table 20.  Reset Signals
Name Width Direction Clock Domain Description
tx_rst_n 1 Input Asynchronous Active-low reset signal.

Resets the GTS Serial Lite IV TX datapath.

rx_rst_n 1 Input Asynchronous Active-low reset signal.

Resets the GTS Serial Lite IV RX datapath.

reconfig_reset 1 Input reconfig_clk Active-high reset signal.

Resets the Avalon® memory-mapped interface reconfiguration block.

tx_reset_ack 1 Output Asynchronous Active-high reset acknowledge signal.

Indicates that soft reset controller has successfully entered reset mode for TX. You can now release the tx_rst_n signal.

rx_reset_ack 1 Output Asynchronous Active-high reset acknowledge signal.

Indicates that soft reset controller has successfully entered reset mode for RX. You can now release the rx_rst_n signal.

src_rs_grant 1 Input Asynchronous Grant signal that allows soft reset controller to perform a reset.

Connect this signal to the o_src_rs_grant output signal of the GTS Reset Sequencer Intel FPGA IP.

src_rs_req 1 Output Asynchronous Request signal from soft reset controller to perform a reset.

Connect this signal to the i_src_rs_req input signal of the GTS Reset Sequencer Intel FPGA IP.