GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

4.4.2. RX Reset and Initialization Sequence

The RX reset sequence for GTS Serial Lite IV Intel® FPGA IP is as follows:
  1. Assert rx_rst_n and reconfig_reset simultaneously to reset the hard IP, MAC, and reconfiguration blocks.
  2. Wait for rx_reset_ack to assert.
  3. Release rx_rst_n after rx_reset_ack, and release reconfig_reset.
  4. Assert rx_cdr_lock.
  5. The IP then asserts the phy_rx_pcs_ready signal after the custom PCS reset is released, to indicate RX PHY is ready for reception.
  6. The IP starts the lane alignment process after the RX MAC reset is released and upon receiving ALIGN paired with START/END or END/START CW. The RX deskew block asserts the rx_link_up signal once alignment for all lanes has complete. The IP then asserts the rx_link_up signal to the user logic to indicate that the RX link is ready to start data reception
Figure 25. RX Reset and Initialization Timing Diagram