GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

6.5. PMA/PCS Signals

Table 24.  PMA/PCS SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description

tx_pll_locked

N Output Asynchronous When asserted, indicates the TX PLL has achieved lock status.

tx_serial_data

N Output TX serial clock TX serial pins.

rx_serial_data

N Input RX serial clock RX serial pins.
phy_rx_block_lock N Output Asynchronous When asserted, indicates that the 66b block alignment has completed for the lanes.
rx_cdr_lock N Output Asynchronous When asserted, indicates that the recovered clocks are locked to data.
phy_rx_pcs_ready N Output Asynchronous When asserted, indicates that the RX lanes of the corresponding Ethernet channel are fully aligned and ready to receive data.
phy_rx_hi_ber N Output Asynchronous When asserted, indicates that the RX PCS of the corresponding Ethernet channel is in a HI BER state.
sys_pll_locked 1 Input Asynchronous Lock signal from the GTS System PLL Clocks Intel FPGA IP, used by HIP for monitoring purposes.

Connect this signal to the o_pll_lock signal of the GTS System PLL Clocks Intel FPGA IP