GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

2.2. Supported Features

The following table lists the features available in GTS Serial Lite IV Intel® FPGA IP:
Table 3.   GTS Serial Lite IV Intel® FPGA IP Features
Feature Description
Data Transfer
  • For NRZ mode:
    • GTS supports 1 Gbps to 16 Gbps per lane with a maximum of 4 lanes.
    Refer to Parameters for more details on the supported transceiver data rates for NRZ mode.
  • Supports continuous streaming (Basic) or packet (Full) modes.
  • Supports low overhead frame packets.
  • Supports byte granularity transfer for every burst size.
  • Supports user-initiated or automatic lane alignment.
  • Supports programmable alignment period.
PCS
  • Uses hard IP logic that interfaces with Agilex™ 5 GTS transceivers for soft logic resource reduction.
  • Supports 64b/66b encoding decoding.
Error Detection and Handling
  • Supports CRC error checking on TX and RX data paths.
  • Supports RX link error checking.
  • Supports RX PCS error detection.
Interfaces
  • Supports only full duplex packet transfer with independent links.
  • Uses point-to-point interconnect to multiple FPGA devices with low transfer latency.
  • Supports user-defined commands.