GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

6.4. Transceiver Reconfiguration Signals

Table 23.  Hard IP Reconfiguration SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description
reconfig_read 1 Input reconfig_clk PMA reconfiguration read command signals.
reconfig_write 1 Input reconfig_clk PMA reconfiguration write command signals.
reconfig_address 18 bits + Ceiling(log2(N)) Input reconfig_clk Specifies PMA Avalon® memory-mapped interface address in a selected lane.

In NRZ mode, each lane has 18 bits and the remaining upper bits refers to the lane offset.

Example, for a 4-lane design:
  • reconfig_address[19:18] set to 00 = address for lane 0.
  • reconfig_address[19:18] set to 01 = address for lane 1.
  • reconfig_address[19:18] set to 10 = address for lane 2.
  • reconfig_address[19:18] set to 11 = address for lane 3.
reconfig_readdata 32 Output reconfig_clk Specifies PMA data to be read by a ready cycle in a selected lane.
reconfig_waitrequest 1 Output reconfig_clk Represents PMA Avalon® memory-mapped interface stalling signal in a selected lane.
reconfig_writedata 32 Input reconfig_clk Specifies PMA data to be written on a write cycle in a selected lane.
reconfig_readdatavalid 1 Output reconfig_clk Specifies PMA reconfiguration received data is valid in a selected lane.
reconfig_byteenable 4 Input reconfig_clk Specifies PMA reconfiguration byte enable signal.