GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

2.5. Resource Utilization and Latency

The resources and latency for the GTS Serial Lite IV Intel® FPGA IP were obtained from the Quartus® Prime Pro Edition software version 24.1.

Table 5.   Agilex™ 5 GTS Serial Lite IV Intel® FPGA IP Resource UtilizationThe latency measurement is based on the round trip latency from the TX core input to the RX core output.
Transceiver Type Variant Number of Data Lanes Mode ALM Dedicated Logic Registers ALUTs Memory 20K Latency (TX core clock cycle)
GTS 16 Gbps NRZ 4 Full 7100 17148 7869 0 74