GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

4.4. Reset and Link Initialization

The MAC, Hard IP, and reconfiguration blocks have different reset signals:
  • tx_rst_n and rx_rst_n reset signals drive the soft reset controller to reset the Hard IP.
  • Reconfiguration block uses the reconfig_reset reset signal.
Figure 23. Reset Architecture