GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

7.1. Reset Guidelines

Follow these reset guidelines to implement your system-level reset.
  • Tie tx_rst_n and rx_rst_n signals together on the system level in order to reset the TX and RX PCS simultaneously.
  • Assert tx_rst_n, rx_rst_n, and reconfig_reset signals at the same time. Refer to Reset and Link Initialization for more information about the IP reset and initialization sequences.
  • Hold tx_rst_n, and rx_rst_n signals low, and reconfig_reset signal high and wait for tx_reset_ack and rx_reset_ack to properly reset the hard IP and the reconfiguration blocks.
  • To achieve fast link-up between FPGA devices, reset the connected GTS Serial Lite IV Intel® FPGA IPs at the same time.