GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

4.4.1. TX Reset and Initialization Sequence

The TX reset sequence for GTS Serial Lite IV Intel® FPGA IP is as follows:
  1. Assert tx_rst_n and reconfig_reset simultaneously to reset the hard IP, MAC, and reconfiguration blocks.
  2. Wait for tx_reset_ack to assert.
  3. Release tx_rst_n after tx_reset_ack, and release reconfig_reset.
  4. The IP then asserts the tx_pll_locked signal after tx_rst_n is released to indicate that the TX PHY is ready for transmission.
  5. The IP starts transmitting IDLE characters on the MII interface once the MAC is out of reset. There is no requirement for TX lane alignment and skewing because all lanes use the same clock. While transmitting IDLE characters, the MAC asserts the tx_link_up signal. The MAC then starts transmitting ALIGN paired with START/END or END/START CW at a fixed interval to initiate the lane alignment process of the connected receiver
Figure 24. TX Reset and Initialization Timing Diagram