GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 8/05/2024
Public
Document Table of Contents

1. About the GTS Serial Lite IV Intel® FPGA IP User Guide: Agilex™ 5 E-Series Devices

Updated for:
Intel® Quartus® Prime Design Suite 24.2
IP Version 4.0.0

This document describes IP features, architecture description, steps to generate, and guidelines to design the GTS Serial Lite IV Intel® FPGA IP using the transceivers in Agilex™ 5 E-Series devices.

Intended Audience

This document is intended for the following users:
  • Design architects to make IP selection during the system-level design planning phase
  • Hardware designers when integrating the IP into their system-level design
  • Validation engineers during the system-level simulation and hardware validation phases

Related Documents

For other documents related to the GTS Serial Lite IV Intel® FPGA IP, refer to the related information.

Acronyms and Glossary

Table 1.  Acronym List
Acronym Expansion
CW Control Word
RS-FEC Reed-Solomon Forward Error Correction
PMA Physical Medium Attachment
TX Transmitter
RX Receiver
NRZ Non-return-to-zero
PCS Physical Coding Sublayer
MII Media Independent Interface
XGMII 10 Gigabit Media Independent Interface