Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

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ID 782461
Date 12/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control the On-board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. Transceiver Designs Status PMA Setting Port Data Type Error Control Run Control
4.2.5. Transceiver Designs x
Status PMA Setting Port Data Type Error Control Run Control 4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMC+ NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab
4.3. Control the On-board Clock through Clock Controller GUI x
4.3.1. Si5391-1 4.3.2. Si5391-2 4.3.3. Si5392 4.3.4. Si5395 4.3.5. Si5332 4.3.6. Si5518
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device Using the Avalon® Streaming Interface x8 Configuration Mode 5.3. Daughter Card
5.3. Daughter Card x
5.3.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Power A.2. Clocks A.3. General Input/Output A.4. Memory Interfaces A.5. Communication Interfaces A.6. Daughter Card A.7. Connectors and Cables
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

4.2.5. Transceiver Designs

The following designs under the Configure menu can be used to run transceiver tests on the development kit board (refer to The Configure Menu section for the full list of designs):

  • QSFP NRZ
  • QSFP PAM4
  • QSFPDD NRZ
  • QSFPDD PAM4
  • SFP NRZ

You can run tests for these designs using the appropriate electrical loopback modules or optical fiber modules according to the selected design. This section describes these options and tests.

Note: The tab title XCVR can be replaced depending on the selected transceiver design used for FPGA configuration. For example, the tab title is replaced with QSFP NRZ, QSFP PAM4, and so on. This tab then becomes accessible.

The controls and options remain the same across these designs except for the Port option (for the QSFP NRZ and QSFP PAM4 designs you can select one of two QSFP x4 ports. For the QSFPDD NRZ and QSFPDD PAM4 designs you are limited to one QSFPDD x8 port. For the SFP NRZ design you can select one of two SFP x1 ports.)

QSFP refers to the module connected to the QSFP56 slots J901 and J906.

QSFPDD refers to the module connected to the QSFPDD slot J45.

SFP refers to the module connected to the SFP+ slots J903 and J904.

The QSFP NRZ design is used here as an example to illustrate the controls and options available for the configured transceiver design.

Figure 11. The QSFP NRZ Tab

The following sections describe controls in the QSFP NRZ tab:

Status

The Status control displays the following status information during the loopback test:

  • PLL Lock: Shows the PLL locked or unlocked state.
  • Pattern Sync: Shows the pattern synced or not state. The pattern is considered synced when the start of the data sequence (PRBS31 sequence in the data type portion of the frame) is detected.
  • Detail: Shows the PLL lock and pattern sync status. The number of the error bits of each channel can be found here.

PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:

  • Serial Loopback: Displays the signal status between the transmitter and the receiver.
  • VOD: Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap:
    • Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of the transmitter buffer.
    • Pre-tap 2: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
    • Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of the transmitter buffer.
Figure 12. QSFP NRZ — PMA Setting

Port

Choose port to switch between two modules, QSFP0 and QSFP1.

Data Type

The Data Type control specifies the type of data pattern contained in the transactions. Select the following available data types for analysis:

  • PRBS7: Pseudo-random 7-bit binary sequences.
  • PRBS15: Pseudo-random 15-bit binary sequences.
  • PRBS23: Pseudo-random 23-bit binary sequences.
  • PRBS31: Pseudo-random 31-bit binary sequences (default).

Error Control

This control displays data errors detected during analysis and allows you to insert errors:

  • Detected Errors: Displays the number of data errors detected in the received bitstream.
  • Inserted Errors: Displays the number of errors inserted into the transmit data stream.
  • Bit Error Rate: Calculates the bit error rate of the transmit data stream.
  • Insert: Insert a one-word error into the transmit data stream each time you click the button. Insert error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.

Run Control

  • TX and RX performance bars: Show the percentage of the maximum theoretical data rate that the requested transactions are able to achieve.
  • Start: This control initiates the loopback tests.
  • Data Rate: Displays the XCVR type and data rate of each channel.
Figure 13. QSFP NRZ — Data Rate

Section Content
The QSFPDD NRZ Tab
The QSFPDD PAM4 Tab
The FMC+ NRZ Tab
The QSFPDD800 PAM4 Tab

Level Two Title