Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

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ID 782461
Date 5/14/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Testing the Functionality of the Development Kit 4.3. Controlling the On-board Clock through Clock Controller GUI 4.4. Monitoring On-Board Power Regulator through Power Monitor GUI 4.5. Identifying Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus® Prime Software 4.1.5. Running the BTS GUI
4.2. Testing the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMC+ NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab
4.3. Controlling the On-board Clock through Clock Controller GUI x
4.3.1. Si5391-1 4.3.2. Si5391-2 4.3.3. Si5392 4.3.4. Si5395 4.3.5. Si5332 4.3.6. Si5518
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the Avalon® streaming interface x8 configuration Mode 5.3. Daughter Card
5.3. Daughter Card x
5.3.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Power A.2. Clocks A.3. General Input/Output A.4. Memory Interfaces A.5. Communication Interfaces A.6. Daughter Card A.7. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.3. General Input/Output

Table 7.   MAX® 10 and FPGA
Schematic Signal Name Description
FP8_GPIO0 Controls the video FMC card PPM up
FP8_GPIO1 Controls the video FMC card PPM down
FP8_GPIO2 MAX10_SI5518_1V2_RSTN
FP8_GPIO3 FP_CPU_RESETN
FP8_GPIO4 USER_RESETN
FP8_GPIO [10:5] Si5518 SPI interface (FPGA interface 1588 clock)
FP8_GPIO [18:11] Any desired bus communication between Agilex™ 7 FPGA M-Series HBM2e Development Kit and MAX® 10
FP8_GPIO19 FMC_PERSTN in RP mode
Other FP8_GPIO Controls the 1588 clock
Table 8.  System MAX® 10
Schematic Signal Name Description
FPGA_3V3_LED0/DS2 Reserved
FPGA_3V3_LED01/DS1 Reserved
FPGA_3V3_LED02/DS3 Reserved
FPGA_3V3_LED03/DS4 Reserved
QFPDD_0_3V3_LED0/DS5 QSFPDD PORT 0 LED0
QFPDD_0_3V3_LED1/DS6 QSFPDD PORT 0 LED1
QFPDD_1_3V3_LED0/DS11 QSFPDD PORT 1 LED0
QFPDD_1_3V3_LED1/DS12 QSFPDD PORT 1 LED1
QFPDD800_3V3_LED0/DS13 QSFPDD800 LED0
QFPDD800_3V3_LED1/DS14 QSFPDD800 LED1
MAX10_USER_LED0 Reserved
OVERTEMP_N/D10,D19 F-Tile die, R-Tile die, core die, board overtemp red LED is on
MAX_CONFIG_DONE/DS10 LED is on when MAX® 10 configuration is done
S12 FPGA_RESETn
S13 HPS_COLD_RESETn
S9 PCIE_PERST_N
S15 USER RESETN
S2 MAX10 (USER_PB0)
S1 MAX10 (USER_PB1)
S21 CLK_SI5392_RST_R_N
S18 CLK_SI5391_2_RESET_N
S23 CLK_SI5391_RESET_N
SW7 Power recycle
QSFPDD_I2C_3V3_EN_N
  • 0: MAX® 10 access to QSFPDD/QSFPDD800 EEPROM
  • 1: Agilex™ 7 M-Series HBM2e access to QSFPDD/QSFPDD800 EEPROM
MAX10_1V8__SI5391_1_RSTN
  • 0: SI5391 U14 RESETN mode
  • 1: Normal (default)
HPS_RESETN
  • 0: HPS RESETN
  • 1: Normal (default)
FMC_12v_EN

0: FMC_12V OFF

1: FMC_12V ON (DEFAULT)
SVID_I2C_EN
  • Before power ok: 0
  • After power ok: S_control_gui[1], =1 by default
PWRGD_DDR5_MAX_RD
  • Before power ok: 0
  • After power ok: 1
MAX10_SI5518_1V2_RSTN (control by FP8)
  • Before power ok: 0
  • After power ok: 1
CLKMUX_OE_1V8_EN

Enable all the clocks on the development kit.

It is always 0.
CLK_SI5392_RST_R_N
  • Before power ok: 0
  • After power ok: 1
Clk_si5391_2_reset_n
  • Before power ok: 0
  • After power ok: 1
usb_disablen
  • 0: external Intel® FPGA Download Cable is inserted
  • 1: no external Intel® FPGA Download Cable inserted
Fx2_resetn
  • 0: On-board Intel® FPGA Download Cable II is under reset
  • 1: 0: On-board Intel® FPGA Download Cable II is out of reset
BOARD_PWR_GOOD_LED/DS15 FPGA Power Good, Agilex™ 7 M-Series HBM2e power sequences are successful and all the power rails on board are good.
MAX_1V2_FPGA_SPARE[7:0]

Reserved GPIO between System MAX® 10 and Agilex™ 7 M-Series HBM2e. All 8 signals have option pull up and pull down, all can be GPIO signals, I2C, SPI bus between MAX® 10 and Agilex™ 7 M-Series HBM2e, or any status, alert, etc signals between MAX® 10 and Agilex™ 7 M-Series HBM2e.

By default all 8 signals have pull up 4.7K.
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