Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

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ID 782461
Date 5/14/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Testing the Functionality of the Development Kit 4.3. Controlling the On-board Clock through Clock Controller GUI 4.4. Monitoring On-Board Power Regulator through Power Monitor GUI 4.5. Identifying Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus® Prime Software 4.1.5. Running the BTS GUI
4.2. Testing the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMC+ NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab
4.3. Controlling the On-board Clock through Clock Controller GUI x
4.3.1. Si5391-1 4.3.2. Si5391-2 4.3.3. Si5392 4.3.4. Si5395 4.3.5. Si5332 4.3.6. Si5518
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the Avalon® streaming interface x8 configuration Mode 5.3. Daughter Card
5.3. Daughter Card x
5.3.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Power A.2. Clocks A.3. General Input/Output A.4. Memory Interfaces A.5. Communication Interfaces A.6. Daughter Card A.7. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide
A. Development Kit Components
B. Additional Information

1.2. Feature Summary

  • Agilex™ 7 FPGA M-Series (AGM039) device in 4700A BGA package
    • Quad-core 64-bit Arm Cortex-A53 hard processor (HPS)
    • 0.8 V VID-adjustable VCC core
    • F-Tile x3, R-Tile x1, and HBM2E
    • F-Tile 32G NRZ (58G PAM4) / High-Speed Transceiver 58G NRZ (116G PAM4) / R- Tile 32G PCIe* (CXL) Lanes
    • 3.9M logic elements (LE)
    • 1.3M adaptive logic modules (ALM)
    • 12.3K digital signal processing (DSP) blocks
  • FPGA configuration
    • Avalon® streaming interface x8 configuration mode support
    • 2 Gb flash for Avalon® streaming interface x8 configuration mode
    • JTAG header for device programming
    • Built-in Intel FPGA Download Cable II for device programming
  • Programmable clock sources
  • Transceiver interfaces
    • PCI Express* ( PCIe* ) x16 interface supporting Gen 5 endpoint connected to a MCIO connector
    • 2x QSFPDD optical module interface connected to F-Tile transceiver
    • 1x QSFPDD 800 optical module interface connected to F-Tile transceiver
    • 16 F-Tile transceiver connect to FMC+ connector
  • Memory interfaces
    • 2 x40 DIMM sockets supporting DDR5-5600
    • 1 x40 DDR5-5600 component interface for HPS processor memory
    • 1 x40 DDR5-5600 component interface for fabric I/O memory
    • 2 X 16 LPDDR5 component, 2 channels and each is 16 bit data line interface
  • Communication ports
    • JTAG header
    • Micro USB on-board Intel FPGA Download Cable II
    • System I2C header
  • Buttons, switches, and LEDs
    • CPU reset push button
    • PCIe* reset push button
    • CXL reset push button
    • HPS reset push button
    • Four dedicated user LEDs
    • Board power good LED
    • BMC MAX® 10 configuration done LED
    • FPGA configuration done LED
  • Heatsink and fan
    • Air-cooled heatsink assembly for FPGA
    • Air-cooled heatsink assembly for 1 port of QSFPDD-800 and 2 ports of QSFPDD and all 3 ports support class 8
    • Red over-temperature warning LED
  • Power
    • PCIe* input power including required 2x4 auxiliary power connector
    • Blue power-good status LED
    • On/Off slide power switch for benchtop operation
    • On-board power and temperature measurement circuitry
  • Mechanical
    • 4.375” x 10.0” board size
  • Operating environment
    • Maximum ambient temperature of 0°C–30°C
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