Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

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ID 782461
Date 5/14/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Testing the Functionality of the Development Kit 4.3. Controlling the On-board Clock through Clock Controller GUI 4.4. Monitoring On-Board Power Regulator through Power Monitor GUI 4.5. Identifying Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus® Prime Software 4.1.5. Running the BTS GUI
4.2. Testing the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMC+ NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab
4.3. Controlling the On-board Clock through Clock Controller GUI x
4.3.1. Si5391-1 4.3.2. Si5391-2 4.3.3. Si5392 4.3.4. Si5395 4.3.5. Si5332 4.3.6. Si5518
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the Avalon® streaming interface x8 configuration Mode 5.3. Daughter Card
5.3. Daughter Card x
5.3.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Power A.2. Clocks A.3. General Input/Output A.4. Memory Interfaces A.5. Communication Interfaces A.6. Daughter Card A.7. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide
A. Development Kit Components
B. Additional Information

3.2. Powering Up the Development Kit

To power up the development kit, follow these steps:

  1. Use the provided 300 W power adapter to supply power through J12 and J3.
  2. After the power adapter is plugged into J12 and J3, and switch S7 is set to the ON position, DS15 LED illuminates, indicating that the board powered up successfully. If the LED (DS15) is not turned ON, it indicates that one of the voltage regulators is not turned on.
    Note:

    All the QSFPDD and QSFPDD800 ports can support up to class 8, meaning each port consumes 18 W. Two power supplies are needed to provide sufficient power for peak performance.

    The Agilex™ 7 FPGA M-Series HBM2e Development Kit can run the loop back test or memory test using only one power adapter connected to J12. Since one power adapter can provide 300 W maximum, the Agilex™ 7 FPGA M-Series HBM2e Development Kit can only run diagnostic tests.

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