F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

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ID 781679
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver 3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive 4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver

This design example demonstrates an Ethernet solution for Agilex™ 7 devices using the F-Tile Triple-Speed Ethernet IP. You can generate the design from the Example Design tab of the Triple-Speed Ethernet IP parameter editor.

To generate the design example, you must first set the parameter values for the IP variation you intend to generate in your end product. Generating the design example creates a copy of the IP. The testbench and hardware design example uses the copy of the IP as the device under test (DUT). If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP variation that you intend.

Note: The testbench demonstrates a basic test of the IP. It is not intended to be a substitute for a full verification environment. You must perform more extensive verifications of your own Triple-Speed Ethernet design in simulation and in hardware.

Section Content
Features
Hardware and Software Requirements
Functional Description
Simulation
Hardware Testing
Interface Signals

Level Two Title