Triple-Speed Ethernet Intel® FPGA IP |
The Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) is instantiated with the following configuration:
- Core Configurations:
- Core Variation: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS
- Interface: MII/GMII
- Use internal FIFO: Selected
- Number of ports: 1
- Transceiver type: FGT
- MAC Options:
- Enable local loopback on MII/GMII: Not selected
- Enable supplemental MAC unicast addresses: Not selected
- Include statistics counters: Selected
- Enable 64-bit statistics byte counters: Not selected
- Include multicast hashtable: Not selected
- Align packet headers to 32-bit boundary: Not selected
- Enable full-duplex flow control: Not selected
- Enable VLAN detection: Not selected
- Enable magic packet detection: Selected
- Include MDIO module (MDC/MDIO): Not selected
- PCS/Transceiver Options:
- Enable SGMII bridge: Not selected
- Enable F-Tile transceiver dynamic reconfiguration (System Clock Mode): Selected
- System PLL Frequency: 805.664062
- Enable datapath Avalon Interface: Not selected
- Enable PMA Avalon Interface: Not selected
|
Client Logic |
Generates and monitors packets sent or received through the IP. |
JTAG to Avalon® memory-mapped interface Address Decoder |
Convert JTAG Signals for Avalon® memory-mapped interface. |
IOPLL |
Generates 125 MHz and 62.5 MHz clocks for Triple-Speed Ethernet. |
System PLL |
Generates 805.664062 MHz PLL clock for FGT transceiver. |