F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

ID 781679
Date 7/08/2024
Public

2.4.1. Testbench

Figure 7. Block Diagram of the 10/100/1000Mb Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver Simulation Testbench

A successful testbench sends five packets and receives the same number of packets. The following sample output illustrates the excerpt of the output:

Figure 8. Simulation Test Result of VCS Simulator
Statistics MAC Tx Path

      — Frames sent in TX path total:      5
      — Tx_good_sent:        5
      — Tx_vlan_sent:         0
      — Tx_stack_vlan_sent:      0
      — Payload_err_sent:        0

Statistics MAC Rx Path — Loopback Test

      — Rx_good_rcvd:        5
      — Rx_vlan_rcvd:         0
      — Rx_stack_vlan_rcvd:      0
      — Rx_fifo_overflow_rcvd:   0
      — Rx_payload_err_rcvd:     0
      — Rx_crc_err_rcvd:         0

-- Loopback Simulation Ended with no Error

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End of Simulation — Break