F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

ID 781679
Date 7/08/2024
Public

2.6. Interface Signals

Table 7.  Interface Signals for 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
Signal Direction Description
pll_refclk0 Input

Reference clock for SYSPLL. Set this clock to 156.25 MHz.

reg_clk Input Clock for configuring CSR registers.
tx_serial_data Output Positive signal for the transmitter serial data.
tx_serial_data_n Output Negative signal for the transmitter serial data.
rx_serial_data Input Positive signal for the receiver serial data.
rx_serial_data_n Input Negative signal for the receiver serial data.