F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

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ID 781679
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver 3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive 4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

1.3. Simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench

Figure 5. Procedure to Simulate Example Testbench
Follow these steps to simulate the testbench:
  1. At the command prompt, navigate to the compilation_test_design folder in your example design:
    cd eth_tse_0_example_design/compilation_test_design
  2. Run the following command:
    quartus_tlg altera_eth_tse.qpf
  3. Navigate to the sim directory:
    cd eth_tse_0_example_design/ex_tse/sim/
  4. Run the IP setup simulation:
    ip-setup-simulation --quartus-project=../../compilation_test_design/altera_eth_tse.qpf
  5. Navigate to the testbench simulation directory:
    cd eth_tse_0_example_design/example_testbench/
  6. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
    Table 4.  Steps to Simulate the Testbench
    Simulator Instructions
    ModelSim* In the command line, type vsim -do run_vsim_2xtbi_pma.do. If you prefer to simulate without bringing up the ModelSim* GUI, type vsim -c -do run_vsim_2xtbi_pma.do.
    Synopsys* VCS* In the command line, type sh run_vcs_2xtbi_pma.sh.
    Xcelium* In the command line, type sh run_xcelium_2xtbi_pma.sh.
  7. Analyze the results. The successful testbench sends five packets, receives the same number of packets, and displays the following message: 
End of Simulation - Break
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