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1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
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1.4. Compiling and Configuring the Design Example in Hardware
To compile the hardware design example and configure it on your Agilex™ 7 device, follow these steps:
- Ensure hardware design example generation is complete.
- In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/altera_eth_tse_hw.qpf .
- On the Processing menu, click Start Compilation.
- After a successful compilation, a.sof file is available in <design_example_dir>/hardwarde_test_design directory. Follow these steps to program the hardware design example on the Agilex™ 7 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Agilex 7 I-Series Transceiver-SoC Development Kit to which your Quartus® Prime Pro Edition session can connect.
- Ensure that Mode is set to JTAG.
- Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.