F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

ID 781679
Date 7/08/2024
Public

4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.08 24.1 22.3.0 Updated Block Diagram of the 10/100/1000Mb Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver Simulation Testbench.
2023.10.02 23.3 22.1.0
  • Added information on hardware support:
    • Added new topics:
      • Compiling and Configuring the Design Example in Hardware
      • Hardware Testing
      • Interface Signals
    • Updated the following topics:
      • Quick Start Guide
      • Directory Structure
      • Features
      • Hardware and Software Requirements
  • Updated OPN number in the following topics:
    • Generating the Design Example topic.
    • Hardware and Software Requirements topic.
  • Added a new Design Constraints topic.
2023.06.26 23.2 22.0.0 Initial release.