F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

ID 781679
Date 7/08/2024
Public

2.4. Simulation

The simulation test case performs the following steps:
  1. Instantiates Triple-Speed Ethernet Intel® FPGA IP and SYSPLL.
  2. Starts up the design example with an operating speed of 1G.
  3. Waits for RX clock and RX alignment to settle.
  4. Sends and receives 5 valid 32-bit data on 1G speed.
  5. Completes the simulation and displays End of Simulation.

When the testbench starts, it waits for rx_pcs_ready to go high. It then sends 5 packets to the TX Avalon® streaming interface and waits for those 5 packets to be received on the RX Avalon® streaming interface.