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1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
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2.4. Simulation
The simulation test case performs the following steps:
- Instantiates Triple-Speed Ethernet Intel® FPGA IP and SYSPLL.
- Starts up the design example with an operating speed of 1G.
- Waits for RX clock and RX alignment to settle.
- Sends and receives 5 valid 32-bit data on 1G speed.
- Completes the simulation and displays End of Simulation.
When the testbench starts, it waits for rx_pcs_ready to go high. It then sends 5 packets to the TX Avalon® streaming interface and waits for those 5 packets to be received on the RX Avalon® streaming interface.