F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide

ID 781679
Date 7/08/2024
Public

2.5.1. Test Procedure

After you compile the Triple-Speed Ethernet Intel® FPGA IP design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools>System Console to launch the system console.
  2. In the Tcl Console pane, type cd hwtest/agx/2xtbi_pma to change directory to <design_example_dir>/hardware_test_design/hwtest/agx/2xtbi_pma.
  3. Type source basic/basic.tcl.
  4. Type list_jtag to display a list of JTAG master indexes that are connected to your board.
  5. Type set_jtag<number_of appropriate_JTAG_master> to select the JTAG master.
  6. Type source hwtest_main.tcl to run the design example in 10 Mbps, 100 Mbps and 1 Gbps Ethernet speed.
A successful test run displays the following message: