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1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices
2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
8. Signals
9. Registers
10. Design Security Recommendations
11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.1. Software Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.2. Hardware Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.3. Downloading and Installing the Design
3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.7.3. Tuning the PI Controller Gains
3.7.4. Controlling the Speed and Position Demonstrations
3.7.5. Monitoring Performance
7.3.6.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs
7.3.6.2. Avalon Memory-Mapped Interface
7.3.6.3. About DSP Builder for Intel FPGAs
7.3.6.4. DSP Builder for Intel FPGAs Folding
7.3.6.5. DSP Builder for Intel FPGAs Design Guidelines
7.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
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7.3.4. Sigma-Delta ADC Interface for Drive Axes
The Drive-on-Chip Design Example sigma-delta ADC interface samples the 20-MHz 1-bit ADC serial input for 3 phase current inputs for each drive axis. A decimating sinc3 filter in the FPGA then low-pass filters the serial input. The sinc3 filter does not require hardware multipliers.
Sinc3 Filter
Figure 26. Sinc3 Filter TopologyThe input samples pass through three integrator stages before decimating by a factor of M. The design reserves every Mth sample and discards M-1 samples. The design passes the reserved samples through three differentiators to produce a final output value.
The pulse-width modulation (PWM) block triggers ADC conversion with a reset signal that resets the filters and control logic. The design calculates:
- The direct-current gain of the sinc3 filter as GainDC = MK (where K = 3 for sinc3).
- The internal bus width of the filters as internal bus width = 1 + Klog2M, to account for word growth in the filter stages
- The output data rate for an input sample rate fS and decimation factor M as data rate = fS/M.
When the settling time satisfies and the ADC conversion completes, the design sends an interrupt to the processor.
The design calculates the performance of N-bit ADC as SNR = 6.02N + 1.76dB, where SNR is the signal to noise ratio. Additional noise in the system affects the performance value. The design calculates the effective number of bits (ENOB) as ENOB = (SINAD - 1.76dB)/6.02, where SINAD is the signal to noise and distortion. The design determines SNR, SINAD, and ENOB by decimation ratio.
The sinc3 filter requires a time period 3× longer than the time period of the output data rate to settle. The standard settings of M=128 keeps the settling time short and a deliver a suitable ENOB of 16bits. By choosing to synchronize sampling to the quiet periods of the PWM waveform, signal quality is acceptable when sampled at 16 kHz despite the theoretical output data rate of 156.2 kHz.
| Decimation (M) | GainDC | Word Size | Bus Width | Data rate (kHz) | Settling Time (µs) | ENOB |
|---|---|---|---|---|---|---|
| 8 | 512 | 9 | 10 | 2500 | 1.2 | 6.4 |
| 16 | 4096 | 12 | 13 | 1250 | 2.4 | 8.9 |
| 64 | 262,144 | 18 | 19 | 312.5 | 9.6 | 13.9 |
| 128 | 2,097,152 | 21 | 22 | 156.2 | 19.2 | 16.4 |
Two Filter Paths
The design has two separate filter paths: a control loop filter path and an overcurrent detection filter path.
The control loop filters are slower but more accurate than the overcurrent detection filters with a software selectable decimation factor of M=128 or M=64. The control loop filters have an offset correction feature for zero-offset correction. The filter output is a signed 16 bit (2's complement) format.
The overcurrent detection filters are faster but less accurate than the control loop filters with a software selectable decimation factor of M=16 or M=8. A software configurable overcurrent output provides a direct output to disable the motor when under hardware control.
The control loop and overcurrent detection filters use the same control bit for decimation selection. The possible selections are:
- control loop M=128, overcurrent M=16
- control loop M=64, overcurrent M=8.
Clocks
The design performs synchronization between the ADC clock and the FPGA system clock at the output stage before the design delivers output data in the Avalon memory-mapped interface agent registers.
The external ADC components require a clock source from the FPGA and return samples synchronous to the FPGA-sourced clock. The same clock within the FPGA drives the ADC filters.
You must apply appropriate timing constraints in the Intel Quartus Prime software project to guarantee correct sampling of the ADC interface data. Base the sampling on the clock to output specification of the ADC.