AN 994: Drive-on-Chip Design Example for Intel Agilex® 7 Devices

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ID 780361
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices 2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices 4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 8. Signals 9. Registers 10. Design Security Recommendations 11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
3.1. Software Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.2. Hardware Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI x
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.3. Tuning the PI Controller Gains 3.7.4. Controlling the Speed and Position Demonstrations 3.7.5. Monitoring Performance
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
4.1. Generating the Platform Designer System 4.2. Compiling the Hardware in the Intel Quartus Prime Software 4.3. Generating and Building the Nios V/g BSP for the Drive-on-Chip Design Example 4.4. Software Application Configuration Files
4.4. Software Application Configuration Files x
4.4.1. Defining a New Motor or Encoder Type 4.4.2. Real Time Operating System Specific Configuration Files
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the GUI
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
7.1. NiosV/g Processor Subsystem 7.2. Control Subsystem 7.3. Drive Subsystem 7.4. Motor and Power Board Model
7.3. Drive Subsystem x
7.3.1. Six-channel PWM Interface 7.3.2. Drive System Monitor 7.3.3. Quadrature Encoder Interface 7.3.4. Sigma-Delta ADC Interface for Drive Axes 7.3.5. Motor Control Modes 7.3.6. FOC Subsystem
7.3.2. Drive System Monitor x
7.3.2.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.3.4. Sigma-Delta ADC Interface for Drive Axes x
7.3.4.1. Offset Adjustment for Sigma-Delta ADC Interface
7.3.6. FOC Subsystem x
7.3.6.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.3.6.2. Avalon Memory-Mapped Interface 7.3.6.3. About DSP Builder for Intel FPGAs 7.3.6.4. DSP Builder for Intel FPGAs Folding 7.3.6.5. DSP Builder for Intel FPGAs Design Guidelines 7.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices
2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
8. Signals
9. Registers
10. Design Security Recommendations
11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices

9. Registers

The Drive-on-Chip Design Example for Intel Agilex 7 devices contain many registers that you can set to control the design.
Table 18.  Six Channel PWM Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x00 - - Reserved - -
0x04 pwm_u [31:15] Reserved - -
[14:0] Phase U PWM switching threshold in PWM clocks 0x0 RW
0x08 pwm_v [31:15] Reserved - -
[14:0] Phase V PWM switching threshold threshold in PWM clocks 0x0 RW
0x0C pwm_w [31:15] Reserved - -
[14:0] Phase W PWM switching threshold threshold in PWM clocks 0x0 RW
0x10 max [31:15] Reserved - -
[14:0] PWM maximum count threshold in PWM clocks 0x0 RW
0x14 block [31:10] Reserved - -
[9:0] PWM blocking (dead time) register threshold in PWM clocks 0x0 RW
0x18 trigger_up [31:15] Reserved - -
[14:0] PWM up count trigger for ADC threshold in PWM clocks 0x0 RW
0x1C trigger_down [31:15] Reserved - -
[14:0] PWM down count trigger for ADC threshold in PWM clocks 0x0 RW
0x20 pwm_direct_interface [31:1] Reserved - -
[0] PWM direct interface control, 1 for direct interface, 0 for Avalon interface 0x0 RW
0x24 to 0x28 Reserved [31:0] Reserved - -
0x2C pwm_hall_en [31:3] Reserved - -
[2:0] PWM hall enable, unused 0x0 RW
Table 19.  Drive System Monitor Control and Status RegistersWrite reserved bits as zero and read as zero. R/W1C bits are read, write a 1 to clear the bit.
Address Name Bits Description Reset Value Access
0x00 control [31:3] Reserved - -
[2:0] Control. Write to this register to request a change of state in the drive system monitor. 0x0 RW
0x04 status [31:12] Reserved - -
[11:9] Current DSM state. 0x0 R
[8] PWM control, upper PWM enable, both. - -
[7] PWM control, lower PWM enable 0x0 R
[6] PWM control, PWM enable - -
[4] mosfet_err_latch 0x0 R/W1C
[3] dc_link_clk_err_latch - R/W1C
[2] Undervoltage status 0x0 R/W1C
[1] Overvoltage status - R/W1C
[0] Overcurrent status 0x0 R/W1C
Table 20.  Quadrature Encoder Interface Control and Status Register.Write reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x00 control [31:3] Reserved. - -
[2] index_capture_en bit. The design captures the count in index capture reg, when index pulse occurs, if this bit is set. 0x0 RW
[1] index_reset_en bit. Count resets on index pulse if this bit is set. 0x0 RW
[0] Direction bit. Reverses the count direction when set. 0x0 RW
0x04 count capture [31:0] Captures current count on each strobe. 0x0 R
0x08 maximum count [31:0] Maximum count. Count resets to zero when it reaches this value. 0x3FFF RW
0x0C count [31:0] Current count value. 0x0 RW
0x10 indexcapture [31:0] Captures current count when index pulse occurs if index_capture_en bit is set. 0x0 R
Table 21.  Sigma-Delta ADC Interface Control and Status Registers

Write reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x0 - - Reserved - -
0x04 offset_u [31:16] Reserved. - -
[15:0] Offset for phase U. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x08 offset_w [31:16] Reserved. - -
[15:0] Offset for phase W. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x0C i_peak [31:10] Reserved. - -
[9:0] Overcurrent detection threshold. 0x0 RW
0x10 control [31:4] Reserved. - -
[3] chk_3_ph: check all 3 current phases 0x0 RW
[2] dec_rate, sinc3 filter decimation rate. When set to 0, the sinc3 decimation rate is M=128 for the control loop and M=16 for overcurrent detection; when set to 1, the sinc3 decimation rate is M=64 for the control loop and M=8 for the overcurrent detection. 0x0 RW
[1] Overcurrent error 0x0 RW
[0] Overvoltage enable 0x0 RW
0x18 status [31:5] Reserved. - -
[6] Overcurrent for phase V 0x0 R
[5] conv_done_v 0x0 R
[4] conv_done_u 0x0 R
[3] conv_done_w 0x0 R
[2] Overcurrent for phase U. 0x0 R
[1] Overcurrent for phase W. 0x0 R
[0] Overcurrent for any phase. 0x0 R
0x1C i_u [31:10] Reserved. - -
[9:0] Current in phase U. 0x0 R
0x20 i_w [31:10] Reserved. - -
[9:0] Current in phase W. 0x0 R
0x24 i_peak [31:10] Reserved. - -
[9:0] Overcurrent detection threshold. 0x0 RW
0x28 i_v [31:10] Reserved. - -
[9:0] Current in phase V. 0x0 R
0x2C offset_v [31:16] Reserved. - -
[15:0] Offset for phase V. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x30 overcurrent_u [31:10] Reserved. - -
[9:0] Overcurrent value for phase U. 0x0 R
0x34 overcurrent_w [31:10] Reserved. - -
[9:0] Overcurrent value for phase V. 0x0 R
0x38 overcurrent_v [31:10] Reserved. - -
[9:0] Overcurrent value for phase W. 0x0 R
0x3C Set IRQ counter [31:3] Reserved. - -
[2:0] IRQ counter to ensure enough IRQ timing, automatically calculated in the software.

0x0

 RW
Table 22.  FOC Subsystem Interface Control and Status Registers

DSP Builder automatically generates the following registers. It provides the address in bytes.
Address Name Bits Description Reset Value Access
0x00 Busy bit [31:1] Reserved. - -
[0:0] When ‘1’ not ready to accept new data. 0x0 R
0x04 DSPBA_Start [31:1] Reserved. - -
[0:0] Toggle bit value once to start 0x0 RW
0x08 Axis_In [31:8] Reserved. - -
[7:0] Dummy – unused set to ‘0’ 0x0 RW
0x0C DSPBA_Ready [31:1] Reserved. - -
[0:0] Output data is ready when Control reg value matches Ready 0x0 R
0x40 Kp_cfg_CFG [31:16] Reserved. - -
[15:0] Kp_cfg input value 0x0 RW
0x44 Ki_cfg_CFG [31:16] Reserved. - -
[15:0] Ki_cfg input value 0x0 RW
0x4C I_Sat_Limit_cfg_CFG [31:16] Reserved. - -
[15:0] I_Sat_Limit_cfg input value 0x0 RW
0x80 Iu_Input [31:16] Reserved. - -
[15:0] Iu input value 0x0 RW
0x84 Iw_Input [31:16] Reserved. - -
[15:0] Iw input value 0x0 RW
0x88 Torque_Input [31:16] Reserved. - -
[15:0] Torque input value 0x0 RW
0x8C phi_el_Input [31:16] Reserved. - -
[15:0] phi_el input value 0x0 RW
0x90 reset_Input [31:1] Reserved. - -
[0:0] Reset - set to '1' to reset 0x0 RW
0xCO Valpha_Output [31:0] V alpha output value 0x0 R
0xC4 Vbeta_Output [31:0] V beta output value 0x0 R
0xD8 Iq_Output [31:16] Reserved. - -
[15:0] Iq output value 0x0 R
0xDC Id_Output [31:16] Reserved. - -
[15:0] Id output value 0x0 R
0xE0 Vu_Output [31:16] Reserved. - -
[15:0] Vu output value 0x0 R
0xE4 Vv_Output [31:16] Reserved. - -
[15:0] Vv output value 0x0 R
0xE8 Vw_Output [31:16] Reserved. - -
[15:0] Vw output value 0x0 R
0xF0 Axis_Output [31:8] Reserved. - -
[7:0] Axis value 0x0 R
0xF8 MaxPWMvalue [31:16] Reserved. - -
[15:0] Maximum voltage 0x0 RW
Table 23.  Motor and Power Board Model Control and Status RegistersDSP Builder automatically generates the following registers. It provides the address in bytes.
Address Name Bits Description Reset Value Access
0x00 Busy bit [31:1] Reserved. - -
[0:0] When 1 not ready to accept new data. The design does not use the debugging feature in normal operation 0x0 R
0x02 DSPBA_Start [31:1] Reserved. - -
[0:0] Toggle bit value once to start, debugging feature, set to 1 in normal operation 0x0 RW
0x0C DSPBA_Ready [31:1] Reserved. - -
[0:0] Output data is ready to use the debugging feature. Unused in normal operation with the direct interface for the motor model. 0x0 R
0x40 Sample_Time_CFG [31:16] Reserved. - -
[15:0] Configuration input value: SampleTime, data type: ufix16_en39 0x0 RW
0x41 Rphase_CFG [31:16] Reserved. - -
[15:0] Configuration input value: Stator Phase resistance [Ohm] 0x0 RW
0x48 inv_Lphase_CFG [31:16] Reserved. - -
[15:0] Configuration input value: Inverse Stator Phase Inductance [1/H] 0x0 RW
0x3C PolePairs_CFG [31:16] Reserved. - -
[15:0] Configuration input value: Pole pairs number 0x0 RW
0x50 Ke_CFG [31:16] Reserved. - -
[15:0] Configuration input value: Back-emf constant kE [Vs/rad] 0x0 RW
0x54 Kt_CFG [31:16] Reserved. - -
[15:0] Configuration input value: Motor torque constant kT's peak phase value 0.07/3*sqrt(2) [Nm/A] 0x0 RW
0x58 inv_J_CFG [31:16] Reserved. - -
[15:0] Configuration input value: Inverse Rotor Mechanical Inertia [1/(kgm^2)] 0x0 RW
0x7C Vabc_range_CFG [31:16] Reserved. - -
[15:0] Configuration input value: Phase voltage ADC scale factor: number per V 0x0 RW
0x80 Va_Input [31:16] Reserved. - -
[15:0] Phase voltage A debugging feature. Unused in normal operation with the direct interface for the motor model. 0x0 RW
0x84 Vb_Input [31:16] Reserved. - -
[15:0] Phase voltage B debugging feature. Unused in normal operation with the direct interface for the motor model. 0x0 RW
0x88 Vc_Input [31:16] Reserved. - -
[15:0] Phase voltage C. debugging feature. Unused in normal operation with the direct interface for the motor model. 0x0 RW
0x8C LoadT_Input [31:16] Reserved. - -
[15:0] Configuration input value: Load torque 0x0 RW

0x90

 Reset [31:16] Reserved. - -
[15:0] Reset signal for the motor model 0x0 RW
0x94 DC_link_V_Input [31:16] Reserved. - -
[15:0] Configuration input value: Motor input voltage 0x0 RW
0x98 DC_link_range_CFG [31:16] Reserved. 0x0 RW
[15:0] Configuration input value: DC link voltage ADC scale factor: number per V 0x0 RW
0xBC Iabc_range_CFG [31:16] Reserved. - -
[15:0] Configuration input value: Phase current ADC scale factor: number per Amp 0x0 RW
0xC0 ia_Output [31:16] Reserved. - -
[15:0] Phase current A debugging feature. Unused in normal operation with the direct interface for the motor model. 0x0 R
0xC4 ib_Output [31:16] Reserved. - -
[15:0] Phase current B debugging feature. Unused in normal operation with the direct interface for the motor model. 0x0 R
0xC8 ic_Output [31:16] Reserved. - -
[15:0] Phase current C debugging feature. Unused in normal operation with the direct interface for the motor model. 0x0 R
0xD8 dTheta_dt_Output [31:16] Reserved. - -
[15:0] Angular velocity of the motor's shaft in radians per second. 0x0 R
0xDC ThetaMech_Output [31:16] Reserved. - -
[15:0] The mechanical angle of the motor's shaft. 0x0 R
Level Two Title