AN 994: Drive-on-Chip Design Example for Intel Agilex® 7 Devices

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ID 780361
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices 2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices 4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices 8. Signals 9. Registers 10. Design Security Recommendations 11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
3.1. Software Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.2. Hardware Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI x
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Intel Agilex 7 Devices 3.7.3. Tuning the PI Controller Gains 3.7.4. Controlling the Speed and Position Demonstrations 3.7.5. Monitoring Performance
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
4.1. Generating the Platform Designer System 4.2. Compiling the Hardware in the Intel Quartus Prime Software 4.3. Generating and Building the Nios V/g BSP for the Drive-on-Chip Design Example 4.4. Software Application Configuration Files
4.4. Software Application Configuration Files x
4.4.1. Defining a New Motor or Encoder Type 4.4.2. Real Time Operating System Specific Configuration Files
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the GUI
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices x
7.1. NiosV/g Processor Subsystem 7.2. Control Subsystem 7.3. Drive Subsystem 7.4. Motor and Power Board Model
7.3. Drive Subsystem x
7.3.1. Six-channel PWM Interface 7.3.2. Drive System Monitor 7.3.3. Quadrature Encoder Interface 7.3.4. Sigma-Delta ADC Interface for Drive Axes 7.3.5. Motor Control Modes 7.3.6. FOC Subsystem
7.3.2. Drive System Monitor x
7.3.2.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.3.4. Sigma-Delta ADC Interface for Drive Axes x
7.3.4.1. Offset Adjustment for Sigma-Delta ADC Interface
7.3.6. FOC Subsystem x
7.3.6.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.3.6.2. Avalon Memory-Mapped Interface 7.3.6.3. About DSP Builder for Intel FPGAs 7.3.6.4. DSP Builder for Intel FPGAs Folding 7.3.6.5. DSP Builder for Intel FPGAs Design Guidelines 7.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices
2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
8. Signals
9. Registers
10. Design Security Recommendations
11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices

4.4. Software Application Configuration Files

You can modify the operation of the software application for the Drive-on-Chip Design Example by editing some C source code and header files.
Table 1.  Software application configuration files
File Path Function
demo_cfg.c . Declare motors[] array
demo_cfg.h . Configuration macros and include file for demo_cfg.c
motor_types.c Platform/motors Declares motor types and encoders
motor_types.h Platform/motors Defines motor and encoder types and include file for motor_types.c
app_cfg.h . Header file for OS cfg switches

Table 2.  Configuration MacrosThis table lists the configuration macros that you can use to configure the design in demo_cfg.h.
Macro Default State Range Function
FIRST_MULTI_AXIS 0 0 - 1 Index of first motor axis to be controlled.
LAST_MULTI_AXIS 1 0 - 1 Index of last motor axis to be controlled.
DEFAULT_ADC_TYPE ADC_TYPE_SIGMA_DELTA ADC_TYPE_SIGMA_DELTA Use sigma delta ADCsamples in control loop.
SD_ADC_FILTER ADC_D_10US ADC_D_10US Sinc3filter delay 10us.
ADC_D_5US[VVE1] [WS2] Sinc3filter delay 20us.
constScaleVoltage 1<<6 n Voltage is stored as short (16 bits signed value:sfix16), (1<<n), n means how many decimal bit in sfix16
OPEN_LOOP_INIT 0 0 Start motors in closed loop mode.
1 Start motors in open loop mode.
INTERACTIVE_START 0 0 Normal startup 1:
1 User prompted via Nios V/g console at each stage of startup
PWM_DEAD_TIME_NSEC 2000[VVE3] [WS4] This is the dead period between switching of the upper and lower power transistors.
SENSORLESS_STARTUP_COUNT 6400UL Count in sample periods to run in open loop before switching to sensor less.
MOTION_TMR_PERIOD 1 Period (in OS ticks) for speed or demo timer
DBG_DEFAULT DBG_INFO DBG_NEVER No console output.
DBG_ALWAYS Always output.
DBG_FATAL Debug level set to fatal errors.
DBG_ERROR Debug level set to non-fatal errors and above.
DBG_WARN Debug level set to warnings and above.
DBG_INFO Debug level set to information and above.
DBG_PERF Debug level set to performance data and above.
DBG_DEBUG Debug level set to debug messages and above.
DBG_DEBUG_MORE Debug level set to more debug messages and above.
DBG_ALL Debug level set to all messages.

Section Content
Defining a New Motor or Encoder Type
Real Time Operating System Specific Configuration Files

Level Two Title